Register File with low power retention mode and 3 speed options
ChipIdea's Analog Front-End for Power Line Communications Modem sucessfully integrated in INSONET transceiver chip
Update: MIPS Technologies Acquires Chipidea (August 27, 2007)
February 4, 2003 - Following the silicon verification of ChipIdea's Analog Front-End for Power Line Communications, the core was further enhanced and integrated with a powerfull OFDM BaseBand processor into a single chip. Test results show improved performance over the first silicon version.
Chipidea's Analog Front-End solution for Power Line Communications is a macro-block with I/Q receive and transmit port that includes signal conversion, filtering, frequency translation, and synthesis functions necessary to interface an OFDM baseband processor to the Power Line.
Associated INSONET technology has demonstrated up to 10Mbps over Power Lines, with a 4.268MHz OFDM signal bandwidth flexibly allocated between 10MHz to 30MHz.
Test results show the transmitter achieving up to 56dB SFDR and 47dB SINAD. The receiver performance exceeds 54dB SINAD.
Current consumption, for a 3.3V power supply, is around 200mA in full operation.
This CI7118ja block has been designed in 0.35um CMOS technology, and is retargetable towards any sub-micron CMOS technology with 2.5V/ 3V/ 5V supply, with double poly option.
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