DMP releases IP Core "ZIA ISP"
Juy 13, 2020 -- Digital Media Professionals Inc. (Headquarters: Nakano-ku, Tokyo, President & COO Tsuyoshi Osawa, hereinafter referred to as DMP) is pleased to announce the release of the ISP (Image Signal Processor) IP core "ZIA™ ISP" (hereinafter referred to as "ZIA ISP"). ZIA ISP contributes to higher image quality and higher performance of AI camera devices such as robotic vehicles, drones, and security cameras.
ZIA ISP is an IP core that performs image processing on the RAW data output from an image sensor. ZIA ISP accelerates the camera signal processing pipeline in a small size, which performs correction processing for the optical system such as lenses and scratch correction caused by variations in the image sensor for each pixel unit. In addition, by supporting a RCCB sensor, the dynamic range expansion by C pixels and HDR makes it easier to detect the contours of objects and people, especially in high and low brightness subjects. Since the user interface supports the AMBA AXI interface, it can be easily embedded in ASIC or FPGA. ZIA ISP can be used as an independent IP core, but by combining it with DMP's AI processor "ZIA™ DV720", a highly accurate and highly efficient image recognition solution can be realized.
Ad |
8-13M pixel sensor support High Quality Image Signal Processing (ISP) IP UHD Image Signal Processing (ISP) Pipeline |
Outline of features and functions of "ZIA™ ISP"
- Demosaic
- Defective pixel correction
- Scaler
- Format conversion
- Gamma correction
- Auto White Balance/Auto gain/Auto exposure
- Frame buffer write
- RCCB sensor compatible
- Interface: MIPI CSI-2
- Supported resolutions: UHD 3840x2160@60fps
- Supported format: RAW Bayer/RGB/RCB
- BUS interface: AMAB AXI
- Supported hardware: ASIC、FPGA
Product availability
Available from 2020/07/13 (already started providing some customers)
Assumed application
Robotic vehicle, safe driving support system, drone, security camera, etc.
DMP will continue to contribute to the development of customers' edge AI applications by providing IP and module products.
About Digital Media Professionals Inc. (DMP)
DMP is an R&D-type fabless semiconductor vendor that deploys licensing business of hardware IPs and software IPs based on proprietary 2D/3D graphics technology for embedded devices, as well as graphics LSI business that incorporates these IPs. In recent years, in order to become the world's leading "AI Computing Company", DMP provides solutions through a broad portfolio including AI processor IPs, hardware/software products and services, and AI ecosystem established by its own.
|
DMP Inc. Hot IP
Related News
- DMP releases AI Processor IP Core "ZIA DV740"
- DMP Released Next-Generation AI Accelerator IP "ZIA A3000 V2" - Industry-leading PPA efficiency to propel the future of edge AI
- DMP AI Processor IP "ZIA DV700" Enables AI at the Edge
- ASICFPGA releases new ISP core supporting AXI4-Lite, AXI4-Stream, new AE, and new AWB
- DMP Launches "ZIA SV" Stereo Vision IP for AMD Xilinx Adaptive Computing Devices
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |