Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO
Henderson, NV, USA – July 22, 2020 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a RISC-V focused static verification rule set to ALINT-PRO™; rules that statically validate HDL code quality prior to simulation.
Based on industry best-practice coding techniques and Aldec’s 36 years of verification experience, the new RISC-V rule set helps designers statically verify home-grown RISC-V designs, as well as helping IP integrators select and properly integrate open-source RISC-V cores into their SoCs.
The new RISC-V rule set includes:
- Coding styles. This set verifies the correct use of constants and variables, port definitions, instantiations, and object references.
- Data types and operations. This set verifies correct Verilog and SystemVerilog data types usage in expressions. For example, the rules provide array index-to-bounds checks, warn about mixing signed and unsigned signals (in any single expression), and bit width mismatches.
- Coding for implementation. This set contains important code checks for optimal synthesis, timing closure (for resets as well as clocks) and Finite State Machine implementation.
- SystemVerilog constructs. This set ensures optimal SystemVerilog usage for the RTL coding. Checks are applied on instantiations and interfaces on SystemVerilog types and procedural blocks.
“Using commercial IPs, the latest industry data shows that more than 50% of the total FPGA/ASIC project time is spent in verification, and more than 40% of that time is spent in debugging errors and functional flaws,” said Louie De Luna, Director of Marketing. “Using open-source IPs such as RISC-V open-source cores may increase the verification and integration effort even more - and this is the main reason we created the RISC-V rule set. Running static verification prior to RTL simulation and logic synthesis stages prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to fully verify the design.”
Zibi Zalewski, General Manager of Aldec’s Hardware Division, commented: “We all know the score with open-source IPs - its maturity and therefore value depend heavily on the verification effort. While ISA compliance confirms the specification of the RISC-V IP has been met, we can provide further quality assurance through the new RISC-V rule set we’ve added to ALINT-PRO.”
ALINT-PRO 2020.07 is now available for download and evaluation.
About ALINT-PRO
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, avoiding problems on further design stages, clocks and reset tree issues, CDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically.
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
|
Related News
- UltraRISC Selects Valtrix STING for Verification of RISC-V SoC Designs
- Imperas Donates Latest RV32/64K Crypto (scalar) Architectural Validation Test Suites to the RISC-V Verification Ecosystem
- Axiomise Announces the Release of the Next-Generation RISC-V App
- Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO for DO-254 Projects
- SiFive Selects Synopsys Verification Continuum Platform for Advanced RISC-V Processor Designs
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |