Xilinx Delivers HyperTransport Lite Reference Design Using Broadcom Silicon

Xilinx Virtex-II Platform FPGAs and Broadcom's MIPS-based processors enable rapid development of Gigabit internet protocol products

SAN JOSE, Calif., February 5, 2003 -Xilinx, Inc. (NASDAQ: XLNX) today announced the immediate availability of a minimal HyperTransport™ (HT-Lite) reference design using the Xilinx® Virtex-II™ Platform FPGAs. Leveraging Xilinx's flexible SelectI/OTM-Ultra technology with Broadcom's minimal HyperTransport IP, the Virtex-II FPGA acts as a bridge to provide seamless connectivity between BroadcomÒ MIPS™-based processors and ASSPs. This HT-Lite reference design enables engineers to rapidly develop designs utilizing Broadcom MIPS-based processors.

Today's news underscores the companies' commitment to a technology relationship aimed at providing interoperable interfaces for use in communications, networking, and consumer applications. The HT-Lite reference design is one of several efforts resulting from Broadcom's membership in the Xilinx Reference Design Alliance Program.

"The reference design demonstrates how HyperTransport technology can provide seamless connectivity for next-generation networks," said Gabriel Sartori, president of the HyperTransport Technology Consortium. "Collaboration between companies like Broadcom and Xilinx, both HyperTransport Technology Consortium members, will help ensure that the HyperTransport technology satisfies the ever increasing need for bandwidth by providing a universal connection designed to reduce the number of buses within a system, provide a high-performance link for embedded applications, and enable highly scalable multiprocessing systems."

"By combining the highly flexible Xilinx Virtex-II FPGA solution with our MIPS-based processors, original equipment manufacturers (OEMs) can easily add additional features with minimal impact to their design schedules," said Krishna Anne, Strategic Marketing Manager of Broadcom's Broadband Processor Business Unit.

Price and Availability
The HT-Lite reference design is used for a slave interface to end an HT chain, supporting an 8-bit link width at a design speed of 400 MHz DDR (800 Mbps per I/O). The HT-Lite core uses less than 1900 slices in a Virtex II FPGA to provide customers with a low-cost HT alternative. The HT-Lite reference design is available now free of charge. Documentation and instructions for downloading the reference design can be found at: http://www.xilinx.com/xapp/xapp639.pdf. Customers in need of a full-featured solution can use the full HT core which is also available now at: http://www.xilinx.com/ipcenter/.

Xilinx Reference Design Alliance Program
The Xilinx Reference Design Alliance Program (www.xilinx.com/reference_design) builds partnerships with industry leading semiconductor and design companies to develop reference designs for accelerating product development and improving time-to-market. The reference designs are ideal for a wide variety of electronic systems, including networking, communications, video imaging, DSP, optical interface, and emerging market applications.

About Xilinx
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com.

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