7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Exostiv Labs achieves 50 Gbps interoperability tests with Avnet ONIX board.
July, 27th, 2020 -- Wavre, Belgium and Bnei Dror, Israel -- Exostiv Labs has successfully completed a round of advanced interoperability tests with Avnet’s ONIX ASIC prototyping system, equipped with the Xilinx Virtex Ultrascale XCVU440 FPGA.
Avnet’s ONIX ASIC prototyping system, co-developed by Avnet and Dgtronix, was successfully used with Exostiv Dashboard for Xilinx FPGA. This setup allowed collecting up to 8 GByte of debug trace from Virtex Ultrascale running at speed through transceivers. The system provided more 50 Gbps total bandwidth over FMC connectivity with Exostiv probe.
‘We are very satisfied with this result, Frederic Leens, CEO of Exostiv Labs says. Speed of setup and overall visibility are critical for ASIC prototyping on FPGA and complex high-speed applications such as low latency Ethernet and acceleration. Not only did Avnet’s board interoperate right away with Exostiv probe, but it provided up to 50 Gbps total bandwidth for collecting debugging trace “out of the box” from its FMC connectors.”
With its library of plug-in boards and its modular architecture, ONIX provides a flexible environment for FPGA-based prototyping of ASIC and SoC. As a board, and technology-independent tool, EXOSTIV complements this environment by adding unprecedented visibility into the chip.
‘Visibility is essential to FPGA-based prototyping’, Itamar Kahalani, FAE at Avnet says. “Exostiv’s impressive performance goes much beyond what other instrumentation solutions are capable of, in terms of the number of internal data nodes, trace depth and ability to visualize exceptionally large capture data sets. Exostiv is the ideal EDA tool for ONIX because it makes the most of the ASIC prototype’.
The ONIX ASIC prototyping platform is designed for rapid prototyping and ASIC emulation of high-performance, high-complexity systems. It is available through Avnet Silica across EMEA and Avnet Worldwide.
For more information and a demonstration:
https://www.exostivlabs.com/fpga-prototyping-platform-gets-visibility-with-exostiv/
|
Related News
- Exostiv Labs Unveils AMD Versal Adaptive SoC Device Support for Exostiv and Exostiv Blade Platforms
- Synopsys Demonstrates Industry's First PCI Express 5.0 IP Interoperability with Intel's Future Xeon Scalable Processor
- eInfochips provides SOC engineering services to Astera Labs in developing industry's first PCIe 4.0 & 5.0 Smart Retimer SoC.
- Rambus Achieves Industry-Leading GDDR6 Performance at 18 Gbps
- Astera Labs Accelerates PCI Express 5.0 System Deployment in Collaboration with Intel and Synopsys
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |