Spin Memory Unveils New Method of Designing Memory to Shake Up $100B Chip Market

Universal Selector Technology Brings DRAM, MRAM and Other Memories to Higher Densities than Predicted by Moore’s Law

FREMONT, Calif. – August 12, 2020 - Spin Memory, Inc. (Spin Memory), the leading developer of MRAM technologies, today announced a new solution that will significantly improve the capabilities of existing and emerging memory technologies: the Universal Selector. As the cost of semiconductor scaling and innovation continues to rise, the industry has struggled to make major advances in scaling and performance — which limits advancements in areas such as AI and IoT.

Spin Memory’s new Universal Selector creatively solves this problem with a novel approach to how transistors are designed and built into memory chips. It is a completely new way of designing dynamic random-access memory (DRAM), magnetoresistive random-access memory (MRAM), Resistive RAM (ReRAM) and other emerging memory technologies — which encompasses more than $100 billion in semiconductor products. The Universal Selector allows on-chip memory to achieve higher levels of performance, reliability and density than ever before, which will boost innovation to levels above that anticipated by Moore’s Law.

The innovation enables new layouts, smaller cell footprints and improved densities in DRAM, MRAM and ReRAM products — bringing about higher levels of performance, reliability and density than ever before. Additionally, the Universal Selector is the first true industry solution to the DRAM problem of row hammer disturbs, while simultaneously reducing Soft Error Rates (SER) and leakage. Spin Memory is currently working with NASA on the applicability of this technology to develop low SER and row hammer-immune DRAM solutions.

“Row hammer is one of the leading issues in DRAM reliability and security, and has long been a frustrating plague on the memory industry. As DRAM’s longstanding major disturb problem, row hammering is only becoming more of a problem as cells shrink,” said Charlie Slayman, IRPS 2020 technical program chair. “Spin Memory’s Universal Selector offers a novel way to design vertical cell transistors and has been presented to the JEDEC task group evaluating solutions to the row hammering problem.”

Spin Memory’s Universal Selector is a selective, vertical epitaxial cell transistor whose channel has a low enough doping concentration that it operates in full depletion. The fully depleted cell transistor along with other unique process and device features leads to a crucial architectural change, allowing the channel to be completely electrically isolated from the silicon substrate. This completely eliminates the possibility of any trapped or migrating electrons causing row hammer, making this design row hammer-immune.

Beyond solving the row hammer disturb problem, the Universal Selector improves DRAM array density by 20% –35% through its 4F² (4F2) DRAM bitcell configuration. For emerging memories such as MRAM, ReRAM and PCRAM, the Universal Selector enables manufacturers to create 1T1R memory bitcells of 6F² – 10F² (6F2 – 10F2), enabling manufacturers to embed up to five times more memory in the same area footprint with minimal additional wafer processing costs. This drastically improved memory density will fulfill the demands of cutting-edge applications — allowing artificial intelligence, virtual reality, edge computing and more to reach new technological heights.

“Today’s most innovative and demanding technologies need more advanced memory to keep up with computing demands. Speed and reliability are necessary for complex applications running at the edge, such as autonomous vehicles or health wearables — where accurate and real-time decisions could make the difference between life and death,” said Tom Sparkman, CEO of Spin Memory. “Our latest breakthrough innovation allows for exciting new advancements and capabilities for these technologies — in addition to pushing MRAM into the mainstream market.”

Beyond the density improvements for DRAM and all emerging memories, Spin Memory’s new Universal Selector will bring MRAM to a new level of SRAM-like performance. Combined with the company’s other MRAM IPs and innovations, including the PSC, Spin Memory is overcoming all the limitations of MRAM to offer a next-generation nonvolatile memory solution for the industry. The emerging hyper-dense, high-performance MRAM will offer a new memory option that overcomes many of the limitations of legacy SRAM solutions for on-chip memory.

Additionally, this new way of building transistors allows for smaller memory cells while utilizing materials and processes that already exist in standard silicon manufacturing processes. This empowers any developer of non-Flash memories to take advantage of the Universal Selector quickly and easily. This breakthrough allows for drastically improved density for almost every memory technology on the market without requiring an investment in specialized hardware or resources.

Spin Memory will share additional technical details on this new technology and solution at the virtual 31st Magnetic Recording Conference on Thursday, August 20 at 10:40 a.m. PDT. Dr. Kadriye Deniz Bozdag, Spin Memory’s manager of MRAM testing, will give an online presentation on the Universal Selector’s full functions and capabilities. Anyone interested in signing up for the event and watching the presentation online can register here.

About Spin Memory

Spin Memory, Inc. is the pre-eminent MRAM IP supplier. Through collaboration with industry leaders, Spin Memory is transforming the semiconductor industry by solving memory challenges vital for AI, ADAS, 5G, IoT and more. Spin Memory’s disruptive STT-MRAM technologies and products provide SRAM-like speed and endurance that can replace SRAM and ultimately DRAM in both embedded and stand-alone applications. For more information, please visit www.spinmemory.com.