ARC: from 3D Game Chips to Licensable RISC Processor
By Nitin Dahad, EETimes (September 21, 2020)
Today marks the 20th anniversary of a landmark in my career, and probably a handful of others. On 21st September 2000, the 32-bit configurable RISC processor company ARC International, now an integral part of Synopsys, completed a major milestone in its history: an IPO (initial public offering) on the London Stock Exchange, at a first day market valuation of around £1.1 billion.
That was a huge achievement for all concerned, but for me it was extra special, because it was the culmination of an objective set by the two people, founder Rick Clucas and CEO Bob Terwilliger, who recruited me as part of the early team of 20 or so people at Argonaut RISC Cores as it was called then, in July 1998. When I visited them for my ‘interview’ in the Argonaut Software building in Edgware, north of London, where there was a large cutout of one the big Nintendo games they’d produced (I believe it was Star Fox) in the lobby, the speed with which startups can make decisions meant I was already offered the ‘job’.
That same evening, pleased that I’d agreed to join, Bob took me to dinner in a well-known Indian restaurant in the center of London, and set me my target: “I want to do an IPO in two years, and you’re going to help us do it,” he told me.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Synopsys' New Superscalar ARC HS Processors Boost RISC and DSP Performance for High-End Embedded Applications
- ARC International Introduces ARC 501 32-bit RISC Processor Core
- Altera and New AMPPSM Partner ARC Cores Announce Configurable RISC Processor For APEX(tm) 20K Devices <!--<FONT SIZE=-1>(by Peter Clarke - EE-TIMES)</FONT>-->
- Palmchip Introduces MP3 Player SOC Hardware Platform with Embedded RISC Processor from ARC
- NEO Semiconductor Announces the Development of its 3D X-AI Chip; Targeted to Replace Existing HBM Chips and Solve Data Bus Bottlenecks
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks