Spectral Design & Test Inc. Announces 3rd Generation 45RFSOI Low Power SRAM Targeted at the 5G Mobile Device SoC Market
SOMERVILLE, N.J. -- Sept. 23, 2020 -- Spectral Design & Test Inc. (SDT), a leading provider of embedded Memory Development platform is announcing immediate availability of a third generation SRAM Memory Compiler in the GlobalFoundries 45 RF SOI process that substantially reduces leakage power by a factor of 35X compared to the standard memory IP in that process. This solution will address the low power requirements of the millimeter wave 5G infrastructure manufacturers who are integrating RF & digital designs on a SOI process.
5G base station and infrastructure is currently being deployed by many customers in the Global Foundries 45nm RF SOI process, this enables customers to integrate the RF Analog and the Digital back planes onto one chip. This Low Power SRAM from SDT will enable migration to battery operated systems.
“Recently we have begun to see a significant increase in interest for low power solutions on the 45 RFSOI node,” said Michael Walton, Vice President of Sales & Marketing at SDT. “To address this market, SDT deployed it’s 3rd generation low power Memory IP Architecture resulting in a significant reduction in active leakage power without any impact on the physical dimensions and only a 30% reduction in speed. Most of our customers rated speed requirements for their applications to be only secondary.” Michael further added, “Upon a survey of a dozen 45-RFSOI customers dynamic leakage & to some extent dynamic power would be a primary concern for their millimeter wave applications.” SDT’s Low power solution also has the option to further reduce dynamic power based on the modalities of usage of the SRAMs in the targeted applications. For customers looking for on-chip test & repair, Spectral offers an option to generate synthesizable RTL that is verified on a Cadence synthesis flow.
SDT is member of the RFwave partnership at Global Foundries providing foundry sponsored Foundation Memory Compilers. They are also a Silver Sponsor of the Global Foundries GTC 2020 Conference that will be held on September 24th. Our Virtual Exhibit Booth will be available during the Conference to provide more detailed information on the latest advances in the high speed low power embedded MemoryIP .
About Spectral Design & Test Inc.
Spectral is a point solution provider specialized in embedded memory development. Our products address the needs of library developers & SOC designers. MemoryCanvas™, our flagship memory development product, offers an ease of use and productivity level unmatched in the industry. MemoryTime™ enables designers to model, analyze, characterize and generate integration views for any embedded memory. Spectral also offers intellectual property (IP) in the form of specialized embedded memories as part of their MemoryIP™ offering. Spectral currently supports customers in several different markets namely medical, IoT, 5G infrastructure and many others. For more information, visit http://www.spectral-dt.com .
|
Spectral Design & Test Inc. (SDT) Hot IP
Related News
- Spectral releases Silicon proven High Speed Low Power SRAM compilers in the 40/45nm CMOS/RFSOI process nodes targeted for a wide range of IOT & 5G Applications
- Spectral Design and Test Inc., Announces a New Family of MemoryIP Targeted at the 5G Market
- Gowin Semiconductor Brings Ultra Low Power Programmable Logic Devices To Market
- Spectral & NSCore Announce Strategic Relationship that Significantly Expands Access and Distribution of MTP/OTP Memory Compilers to accelerate SOC integration of NVRAM & Low Power SRAMs for IOT applications
- Synopsys Low Power Solution Accelerates Time to Market for 3G Mobile IC
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |