Intento Design Expands Analog Automation with IDX-PVT, Eliminating the Need for Design-by-Verification
Bankruptcy in July 2023
Paris -- October 8, 2020 -- Intento Design flagship tool ID-Xplore was introduced in 2015, aimed to assist analog designers in creating correct-by-construction, perfectly sized design in seconds. Fully integrated in the Cadence ADE, ID-Xplore is a technology independent analog design acceleration and migration tool for schematic centric design flows.
ID-Xplore is now successfully implemented in analog flows of large European IDMs, notably STMicroelectronics. Design houses and fabless also benefit from ID-Xplore unique bias and sizing exploration, rapidly finding many typical solutions with various performance gains and tradeoffs.
With the number of corners often reaching thousands, intuitively added “design margin” doesn’t work anymore. Designers spend time in endless loops, just to reach one well centered design with enough margin to cover the performance and satisfy the PVT variation.
IDX-PVT gives the control back to analog designers to quickly determine which of the found typical valid solutions are passing the PVT corners. Worst-case corners are quickly detected thanks to smart design space partitioning algorithms.
ID-Xplore featuring IDX-PVT goes a step further in analog design acceleration. IDX-PVT enables fast and efficient design centering, effectively immunizing chips against process variation.
Raouf Khalil, Design Director explains: “Without IDX-PVT, designer has to go through dozens of iteration to find the design that covers at minimum few hundreds of corners with the lowest power budget and the smallest area. And all that was done manually.”
Even more powerful with this new feature, ID-Xplore/PVT quickly finds perfectly centered robust designs that satisfy performances, power, and area requirements while taking into account the design corners.
|
Related News
- Altair Signs Agreement to Acquire Metrics Design Automation Inc. Expands Footprint in EDA Industry
- Analog Bits Expands Engineering Presence by Opening a Design Center in Europe
- Vidatronic Expands Portfolio of Power Management, Analog, and Security IP with Additional 180 nm to 22 nm Technologies for IoT Applications Available for Licensing
- Thalia Design Automation partners with Sofics to enhance offering for analog circuit and IP reuse
- Mythic Expands Product Lineup with New Scalable, Power-Efficient Analog Matrix Processor for Edge AI Applications
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |