Cadence Pegasus Verification System Certified for TSMC N16, N12 and N7 Process Technologies
Customers using Pegasus Verification System on advanced TSMC technologies can achieve physical verification signoff goals
SAN JOSE, Calif., October 12, 2020 - Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Pegasus™ Verification System has achieved the latest Design Rule Manual (DRM) certification for the TSMC N16, N12 and N7 process technologies. The Cadence® Pegasus Verification System has been successfully validated by TSMC to provide customers with a fast path to meet physical verification signoff goals across several application areas including AI, automotive, processor, data center and IP applications.
To learn more about the Pegasus Verification System, please visit www.cadence.com/go/pegasuscpr.
Customers using the Pegasus Verification System on TSMC’s N16, N12 and N7 processes can sign off chips using the TSMC-certified rule decks, which are available for all the signoff physical verification flows such as the design rule check (DRC), layout versus schematic (LVS), and dummy fill.
“We worked closely with Cadence to deliver this certified Pegasus Verification System across several advanced TSMC processes,” said Suk Lee, senior director of Design Infrastructure Management Division at TSMC. “The result of our ongoing collaboration with Cadence helps our mutual customers meet design cycle time goals and reap the power and performance benefits of our industry-leading process technologies including N16, N12 and N7.”
“The Pegasus Verification System allows customers to massively distribute physical verification jobs on heterogeneous hardware environments without memory or CPU slot limitations, providing optimal support on TSMC’s advanced-process technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our continued collaboration with TSMC on the Pegasus Verification System certification provides customers with confidence that they can attain consistent, accurate results and meet competitive schedules.”
The Pegasus Verification System is part of the broader Cadence digital and signoff full flow, which provides better predictability and a faster path to design closure. It supports Cadence’s Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence.
About Cadence
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
|
Cadence Hot IP
Related News
- Cadence Pegasus Verification System Certified for Samsung Foundry 5nm and 7nm Process Technologies
- Cadence Physical Verification System Qualified for TSMC 28nm, 20nm Process
- Cadence Digital and Custom/Analog Design Flows Certified for TSMC's Latest N3E and N2 Process Technologies
- Cadence Design IP portfolio in TSMC's N5 Process Gains Broad Adoption Among Leading Semiconductor and System Companies
- Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |