Arm partners with Mentor to offer complete verification service
By Ciarán Dunne, vice president and general manager, Partner Enablement at Arm
October 22, 2020 -- SoC design is a multifaceted process and we are seeing new levels of technological innovation across sectors including automotive, industrial, and healthcare. The complex processor designs that power this technology require more than 100 years of people effort, with a large portion of that time being spent on verification. Regardless of whether it’s a relatively simple low-power device or a highly intricate design for safety critical applications, it’s important that chip-level technology is designed effectively, and verification is one part of the process that cannot be overlooked.
At Arm, we are always looking at how we can help our partners ensure products are launched quickly but without risking quality. Design verification is fundamental, but there is no ‘one size fits all’ solution. Our partners have multiple factors they must consider, such as what they are trying to achieve and in what market.
The RTL verification journey
There are many barriers for developers to overcome, such as product capability and matching advanced features to specific needs, as well as cost and timescales. To help overcome these challenges, Arm is announcing a new RTL Verification Design Review, in collaboration with Mentor, to help partners find the right balance of quality, advanced capability and cost.
Mentor has many years of experience in verification of complex SoC designs, which combined with Arm’s extensive system design expertise provides an invaluable wealth of knowledge. There are three key stages involved in the new RTL Verification Design Review solution, which Arm and Mentor experts will deliver together to our mutual partners:
- Verification Strategy Review
In addition to reviewing the current verification strategy and methodology, Arm and Mentor will provide developers with guidance on proven verification techniques that will efficiently uncover design issues and bugs prior to project completion. This also involves an audit of your current verification process, along with a review of your testbench architecture, in the context of your architectural specification.
- Verification Plan Review
The second stage will explore in detail the design features to be verified and how the verification strategies employed will ensure they are exercised in accordance with the design specification. This will involve a look into the detailed design specification, in addition to a comprehensive review of our partner’s verification plan.
- Verification Closure Review
In the final stage, the implementation of the metrics described in the verification plan/requirements document will be analyzed to ensure they meet their designed intent. Reviews will then be conducted of the verification environment and simulations results.
A Design Review report will be provided at the end of the process, giving a detailed account of the issues, recommendations, and observations made during the review process.
One of the biggest advantages of using Arm is our proven verification models and EDA tool flows, and Arm’s review offering covers every step of the design process, from architecture to physical implementation and power management. Our new RTL Verification Design Review service in collaboration with Mentor has been created to further improve the quality of your design, while shortening design cycles, time-to-market and reducing project risk.
Further information on the new RTL Verification Design Review solution can be found here.
On November 4, Arm will conduct a free webinar entitled “Selecting the Best Design Verification Strategy for Your Design”. Featuring Mentor RTL experts, the webinar will take place at 10am GMT and again at 4pm GMT. Registration is open now.
About Arm
Arm technology is at the heart of a computing and data revolution that is transforming the way people live and businesses operate. Our advanced, energy-efficient processor designs have enabled intelligent computing in 180 billion chips and our technologies now securely power products from the sensor to the smartphone and the supercomputer. In combination with our IoT device, connectivity and data management platform, we are also enabling customers with powerful and actionable business insights that are generating new value from their connected devices and data. Together with 1,000+ technology partners we are at the forefront of designing, securing and managing all areas of compute from the chip to the cloud.
|
Arm Ltd Hot IP
Related News
- Arm China selects Mentor's Questa Verification Solution to enhance power efficiency and speed development of MCU designs
- Mentor Graphics Signs Multi-year Agreement with ARM for Early Access to ARM IP to Accelerate SoC Verification, Implementation and Testing
- Mentor Graphics Adds ARM AMBA 5 AHB Verification IP to Mentor Enterprise Verification Platform
- Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs
- Mentor Graphics Delivers Emulation Solutions for the Verification of ARM Cortex-A9 MPCore-based Products
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |