Synopsys and Samsung Release Certified 3nm Gate-All-Around AMS Design Reference Flow for Early Design Starts
Flow Leverages Innovative Synopsys Custom Design Platform Features to Streamline 3nm Analog and Mixed-Signal Design
MOUNTAIN VIEW, Calif., Oct. 28, 2020 -- Synopsys, Inc. (Nasdaq: SNPS) today announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform. It has been optimized to provide maximum designer productivity for designers of advanced 5G, HPC, AI and IoT applications using the Samsung 3nm GAA process technology.
Complexity at advanced nodes means designers are looking for new methods to shorten design cycles. Through close collaboration, Samsung and Synopsys provide a flow that is optimized to overcome design complexity and provide the best possible productivity for 3nm GAA design. Key features of the flow include in-design electromigration analysis, which shortens design closure time by providing accurate electromigration analysis before the layout is complete. It also includes Live design rule checking (DRC) with Synopsys' IC Validator physical verification solution, enabling layout engineers to quickly check for design rule violations directly from the layout canvas as they work.
The AMS reference flow provides a proven methodology for designing at 3nm GAA process technology. This methodology, which has been validated by Samsung, includes a full set of documented flows and design examples. Covered topics include design entry, circuit simulation, Monte Carlo analysis, noise analysis, RF analysis, aging and EM/IR analysis, parasitic simulation, layout and signoff.
"With the Synopsys AMS Reference flow, designers can quickly deploy 3nm GAA technology for their most demanding applications, such as artificial intelligence, 5G networking, automotive, the Internet of Things and advanced data centers," said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. "The advanced methodologies enabled by Synopsys help our customers and internal IP developers to create analog and mixed-signal designs more efficiently."
The Synopsys Custom Design Platform is based on the Custom Compiler ™ design and layout environment and includes HSPICE® circuit simulator, FineSim® circuit simulator, CustomSim™ FastSPICE circuit simulator, Custom WaveView™ waveform display, StarRC™ parasitic extraction, and IC Validator physical verification. The platform features natively integrated StarRC extraction to provide early feedback of the impact of parasitics on circuit behavior, performance and pioneering visually-assisted layout automation capabilities that simplify creation of advanced-node layout.
"In developing the 3nm GAA AMS Design Reference Flow, Samsung and Synopsys worked together to enable powerful techniques for shortening design cycles," said Aveek Sarkar, vice president of engineering at Synopsys. "As one example, the reference flow with Synopsys includes a novel solution for early electromigration analysis, which substantially shrinks design closure time."
For more on the Synopsys Custom Design Platform, visit https://www.synopsys.com/custom.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing application that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts
- Ansys and Synopsys Accelerate RFIC Semiconductor Design with New Reference Flow for Samsung Technology
- Synopsys Delivers Higher Productivity and Quality for Advanced-Node 5G/6G SoCs on Samsung Foundry's Low-Power Process
- Synopsys and Samsung Foundry Announce Reference Flow for Predictable Execution of ASIL D-Compliant SoC Design for Automotive Applications
- Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |