English
C-DAC Selects Valtrix STING For Design Verification Of RISC-V Based Microprocessors
Valtrix and C-DAC to collaborate to ensure comprehensive verification of highperformance RISC-V microprocessors.
BANGALORE, INDIA, Dec. 8, 2020 -- Valtrix Systems, provider of design verification products for building functionally correct CPU and system-on-chip implementations, announced today that Centre for Development of Advanced Computing (C-DAC), a premier R&D organization of Government of India, has licensed STING for the verification of RISC-V based designs being developed for use in a number of strategic sectors. C-DAC is collaborating with Valtrix to ensure comprehensive verification of the RISC-V processors and SoC designs developed as part of this project.
| Ad |
RISC-V-based SoC template  TSMC CLN5PLVT 5nm Multi Phase DLL - 1200MHz-6000MHz  Compact, efficient 64-bit RISC-V processor with 5-stage pipeline  |
STING's design verification capabilities are perfectly suited to verify these microprocessors, given its ability to generate portable self-checking stimulus across multiple device-under-test environments and to allow users to exercise architectural and micro-architectural features using its test stimulus programming framework.
"We are very excited that C-DAC has selected STING for design verification of the indigenously developed microprocessors," said Shubhodeep Roy Choudhury, CEO of Valtrix. "As more complex RISC-V designs evolve, a highly complete design verification approach becomes imperative to the success of the project. Valtrix's technology has been designed to embody the best test stimulus generation methodologies and is well suited for verification of a wide variety of processors ranging from IoT/embedded to server platforms."
For more information on Valtrix's design verification technology and products, visit https://www.valtrix.in
About Valtrix's STING Design Verification Tool
STING, the flagship product of Valtrix, is a design verification platform for RISC-V based implementations. It can be configured to generate portable bare-metal programs containing selfchecking architecturally-correct test stimulus, which can then be enabled on simulation, FPGA prototypes, emulation or silicon. STING also provides a RISC-V architecture verification suite to provide users an easy ramp into verification readiness.
|
||||||
Related News
- UltraRISC Selects Valtrix STING for Verification of RISC-V SoC Designs
- StarFive Adopts Valtrix STING for Verification of Next-generation RISC-V Processors
- Imperas Expands Partnership with Valtrix to Address Growing RISC-V Verification Market
- Valtrix and Codasip Cooperate on Verification of RISC-V Systems
- Imperas and Valtrix announce partnership for RISC-V Processor Verification
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |