Seagate Designs RISC-V Cores to Power Data Mobility and Trustworthiness
The company built a system on a chip, demonstrating one of the cores as functional in hard disk drives
FREMONT, Calif.-- December 08, 2020 --Seagate Technology plc (NASDAQ: STX) announced that it has designed two processors based on the open RISC-V instruction set architecture (ISA).
Ad |
RISC-V-based SoC template ![]() Low-power 32-bit RISC-V processor ![]() Compact, efficient 64-bit RISC-V processor with 5-stage pipeline ![]() |
One of the open standards-enabled cores is designed for high performance and the other is area-optimized. The high-performance processor has already been built with RISC-V-enabled silicon and demonstrated as functional in hard disk drives (HDDs). The area-optimized core has been designed and is in the process of being built.
Because both processors offer RISC-V security features, the benefits add up to more robust edge-to-cloud data trustworthiness, security, and mobility—all essential in the era when so much data is on the move.
The announcement, made today at the virtual RISC-V Summit 2020, is the first public report on the results of Seagate’s several years of collaboration with RISC-V International.
“Having shipped close to one billion cores over the last year, Seagate has developed significant expertise in system-on-a-chip design,” said Cecil Macgregor, Vice President, Application-Specific Integrated Circuit (ASIC) Development. “We now expanded the capability to add customized RISC-V cores to our portfolio, which is critical to future products. We live in a time of unprecedented growth of enterprise data—and much of this data is in motion. These cores will allow devices to share a common RISC-V ISA. Using open security architectures, they will enable more secure movement of data.”
The high-performance core offers up to triple the performance for real-time, critical HDD workloads versus current solutions. In an initial use case, this core enabled Seagate to dramatically increase the real-time processing power available. The processor paves the way for finer positioning by implementation of advanced servo (motion control) algorithms.
The area-optimized core boasts a highly configurable microarchitecture and feature set. It’s optimized both for footprint and power savings. It powers auxiliary, supporting, or background workloads. It can execute security-sensitive edge computational operations (including next-generation post-quantum cryptography) while targeting a small-footprint implementation of security features over performance.
One of the key use cases for this core is security. A member of OpenTitan, Seagate is committed to open and transparent security.
“We see a significant potential for open, extensible architectures like RISC-V,” said Dominic Rizzo, OpenTitan Project Director and Engineering Lead at Google Cloud. “OpenTitan’s open-source implementation benefits from RISC-V’s open nature, enabling pan-industry transparency, trust,, and silicon security. Because Seagate understands the promise of RISC-V for security, we are excited to collaborate with Seagate on the open-source silicon root of trust we are currently developing.”
The Seagate cores will also accelerate real-time analysis in the data center and at the edge. Such analysis is crucial to the work of scientific communities with mass data needs.
“At Los Alamos National Laboratory, using computational storage to move processing near data has begun to significantly alter the way we analyze data and perform scientific discovery,” said Brad Settlemyer, Sr. Research Scientist at Los Alamos National Laboratory. “By having compute integrated closely with storage we are able to create persistent data transformations that speed up data analysis by 1000-fold. This greatly relieves our primary compute tier from these tasks. We will be continuing our drive toward efficiency gains for our mission needs by partnering with vendors and actively participating in important industry initiatives like computational storage.”
Seagate has determined that solutions on this front tend to involve custom silicon: that's where RISC-V shines.
“Introducing RISC-V to storage devices creates an opportunity to implement application-specific computational capabilities that enable massive parallel computational storage solutions,” said John Morris, Seagate's Chief Technology Officer. “We believe that these architectures support many important use cases that include scientific simulation (for example, weather prediction) as well as the learning part of machine learning.”
For more on Seagate’s RISC-V innovations, visit this page.
About Seagate Technology
Seagate Technology crafts the datasphere, helping to maximize humanity’s potential by innovating world-class, precision-engineered data storage and management solutions with a focus on sustainable partnerships. Learn more about Seagate by visiting www.seagate.com
|
Related News
- SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs
- SignatureIP Networks-on-Chips (NoCs) to Accelerate RISC-V Designs
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
- Rivos Raises More Than $250M Targeting Data Analytics and Generative AI Markets
- The SHD Group Has Released a Complimentary Version of the 2024 RISC-V Market Analysis Report Containing Current Market Data and Future Projections
Breaking News
- Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applications
- Quadric Announces Lee Vick is New VP Worldwide Sales
- Siemens delivers certified and automated design flows for TSMC 3DFabric technologies
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |