CXL gathers speed with 2.0 spec
Running over PCIe physical layer makes open interconnect easier to adopt
By Gary Hilson, EETimes (January 25, 2021)
TORONTO — The Compute Express Link (CXL) specification is forging ahead at a steady pace. Version 2.0 of the open industry-standard interconnect is now available less than two years after its initial inception, while consortium member vendors already releasing products using the latest iteration.
Like the now mature Non-Volatile Memory Express (NVMe) interface specification, CXL 2.0 is adding new features and functionality to meet increased performance demands while staying backwards compatible with its predecessors — CXL 1.0 was released in March 2019 and 1.1 was announced in June of the same year. Updates in 2.0 are being driven by rapidly evolving datacenter architectures that must support the growing demands of emerging workloads for artificial intelligence (AI) and machine learning (ML). The continued proliferation of cloud computing and the “cloudification” of the network and edge are also factors.
E-mail This Article | Printer-Friendly Page |
Related News
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores with Superfast speed and High-power efficiency for lag-less data processing is Silicon Proven and available in 8nm LPP for licensing
- Avery Design Debuts CXL 2.0 System-level VIP Simulation Solution
- PLDA Announces a Unique CXL Verification IP Ecosystem, Delivering Robust Verification That Reduces Time-to-Design for CXL 2.0 Applications
- Avery Design Announces CXL 2.0 VIP
- Mobiveil Announces Compute Express Link (CXL) 2.0 Design IP, Successful Completion of CXL 1.1 Validation with Intel's CXL Host Platform
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity