AccelerComm Unveils Fully Integrated PUSCH Decoder to Supercharge 5G NR for Performance-Critical Channels
Southampton, UK and MWC Shanghai, China – February 24, 2020 -- AccelerComm, the channel coding specialist, are supercharging 5G NR with cutting edge Physical Layer IP which increases spectral efficiency and reduces latency. The company today announced a complete high-performance 5G NR PUSCH (Physical Uplink Shared Channel) Decoder and PDSCH (Physical Downlink Shared Channel) Encoder for customers who want to maximize the efficacy of their 5G radio network.
Building on the company’s carrier-grade portfolio of channel coding and modulation/ demodulation IP, this highly integrated solution enables 5G base stations to benefit from AccelerComm’s proven best-in-class LDPC decoder performance, whilst minimizing time to market.
“This product builds on the existing AccelerComm IP portfolio to enable operators to deliver on the high-performance, low-latency promise of 5G using their existing spectrum and cloud RAN infrastructure." said Robert Barnes, VP Sales & Marketing of AccelerComm.
AccelerComm’s PUSCH Decoder integrates additional 3GPP physical layer functions together with its high-performance LDPC decoders, to create a 3GPP-compliant IP package that can be quickly integrated and optimized for use in custom silicon (ASIC) and programmable hardware (FPGA).
The flexible architecture means that it can be customized depending on an operator’s service requirements, resulting in optimal performance, power, and silicon area, tailored to their specific needs.
This latest product from AccelerComm adds three new blocks of IP to complete the link between the LDPC decoder and the MIMO detector:
- gNodeB uplink stack (PUSCH Decoder)
- LDPC decoder with transport block wrapper, polar decoder, demultiplexer, descrambler and QAM demodulator
- gNodeB downlink stack (PDSCH Encoder)
- LDPC encoder with transport block wrapper, scrambler and QAM modulator
The specification is as defined in Sections 6.2 and 7.2 of 3GPP document TS 38.212, as well as Sections 6.3.1.1, 6.3.1.2, 7.3.1.1 and 7.3.1.2 of TS 38.211.
|
AccelerComm Limited Hot IP
Related News
- AccelerComm Launches PUSCH Channel Simulator for 5G L1 Performance Evaluation
- AccelerComm Announces 5G PUSCH Channel Equalizer
- AccelerComm secures £21.5m funding to supercharge 5G radio performance
- AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding
- AccelerComm introduces improved channel equalisation for 5G NR at MWC Barcelona 2020
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |