SiPearl passes a key milestone for Rhea's launch by moving into an accelerated simulation phase with Siemens' Veloce platform
Maisons-Laffitte (France) and Duisburg (Germany) -- March 11, 2021 – SiPearl, the company that is designing the high-performance, low-power microprocessor for the European exascale supercomputer, has just passed a key milestone for the launch of Rhea, its first generation of products, in 2022.
While Rhea’s design is progressing well and on track, SiPearl is moving into an accelerated simulation phase on the hardware emulation platform developed by Siemens. SiPearl selected this innovative, state-of-the-art solution after an extensive evaluation because it offers a comprehensive and flexible high-speed, high-capacity verification environment. This enables SiPearl to accelerate the pre-silicon functional verification process in a virtual environment thus validating Rhea’s capabilities before it moves into production.
Siemens’ Veloce™ Strato emulation platform has capacity scaling up to 15B Gate; and with fast compilation, full design visibility, low cost of ownership, it is overwhelmingly the solution of choice for many semiconductor companies, including SiPearl, to verify the largest and most advanced chip designs.
SiPearl will then open up possibilities for its future clients to access the platform to carry out multi-scale performance tests with Rhea for their applications in diverse fields, from fluid dynamics to climatology (global warming), medical research (covid-19), geo-sciences (geology, earthquakes) and artificial intelligence.
“Thanks to our collaboration with Siemens, as we prepare for Rhea’s arrival on the market, we are able to benefit from a powerful and flexible emulation infrastructure, combined with the team’s expertise, which enables us to accelerate its simulation with uncompromised visibility and debug. This technological choice also sets out our strong commitment to our future clients with a view to supporting their own performance levels,” concludes Philippe Notton, SiPearl’s CEO and founder.
About SiPearl
Created by Philippe Notton, SiPearl is the Franco-German company that is bringing to life the European Processor Initiative (EPI) project, designing the high-performance, low-power microprocessor for the European exascale supercomputer.
This new generation of microprocessors will enable Europe to set out its technological sovereignty on the strategic markets for high performance computing, artificial intelligence and connected mobility.
SiPearl is developing and will market its solutions through close collaboration with its 26 partners from the EPI - scientific community, supercomputing centres and leading names from the IT, electronics and automotive industries - which are its stakeholders and future clients. It is supported by the European Union.
SiPearl is also a member of the Mont-Blanc 2020 consortium to equip Europe with a dedicated modular and energy-efficient high performance computing microprocessor, and is a member of the PlayFrance.Digital collective for Europe to lead the field for digital technology.
|
Related News
- MIPS Leverages Siemens' Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor
- Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
- Marvell Announces Industry's First 2nm Platform for Accelerated Infrastructure Silicon
- Siemens' breakthrough Veloce CS transforms emulation and prototyping with three novel products
- Cadence Unveils Millennium Platform - Industry's First Accelerated Digital Twin Delivering Unprecedented Performance and Energy Efficiency
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |