7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
DCD-SEMI gains new strength in the Virtual Reality World with their latest IrDA DIRDA IP Core
Bytom -- April 9, 2021 -- DCD-SEMI, a sister company of well-known DCD (Digital Core Design), leading IP Core provider since 1999, introduces its latest IrDA IP, the DIRDA.
DIRDA performs serial‐to‐parallel conversions on data received from the IR Receiver Diode. The processor can read the complete status of the DIRDA in one cycle and at any time, during the functional operation. DCD-SEMI’s IP Core includes a programmable internal pre-scaler, which can divide the timing reference clock input, by divisors of 1 to 128, and produce a clock for driving internal receiver logic.
DIRDA is equipped with a fully programmable processor‐interrupt system that accelerates response time and minimizes power drain to increase the customers product battery life through minimal compute cycles required to handle the communications link.. - explains Jacek Hanke, DCD-SEMI’s CEO – DIRDA is IrDAs turbo charger.
DCDs DIRDA extremely fast, low power, low voltage solution is poised for prominence in virtual worlds to handle sophisticated sensor data for VR headsets, 360-degree cockpits, games, and videos. – stated Jacek Henke
The DIRDA IP Core can be provided with a small 8‐bit SRAM-like interface and APB slave interface. In MODE0 DIRDA decodes the whole IR frame, detects transmission errors, and key release.
In MODE1, internal FIFO is activated, allowing 32 symbols to be stored during signal receive. The interrupt trigger level register may be set at any value from 1 to 32 symbols. These features make the DIRDA an ideal choice for very popular IR protocol implementations like NEC, SIRC, Toshiba TC9012 data format, or other non‐standard IR protocols.
Key Benefits:
- Enabling and disabling controller via register
- Two working modes:
- MODE0 ‐ standard IR protocols decoding
- MODE1 ‐ symbols width detection for any standard or non‐standard IR data format
- Support for any configuration of the following protocols (MODE0):
- NEC with Simple Repeat Code
- NEC with Full Repeat Code
- Toshiba TC9012 data format
- SIRC (SONY)
- Support for masked and not masked interrupts:
- Symbol overflow interrupt (MODE1)
- Symbol timeout interrupt (MODE1)
- Symbol received interrupt (MODE1)
- Key release interrupt (MODE0)
- Data overflow interrupt (MODE0)
- Data frame format error interrupt (MODE0)
- Data received interrupt (MODE0)
- Interrupts flags clearance via write to register
- Configurable reset
- Configurable data bus width
- Reference clock frequency in the range of 1MHz‐128MHz
More information: www.dcd-semi.com
|
Digital Core Design Hot IP
Related News
- Digital Core Design in cooperation with DCD-SEMI Unveils DCAN-XL: Revolutionary CAN XL IP Core Bridging the Gap Between CAN FD and Ethernet
- BrainChip's Latest US Patent Award Extends Intellectual Property Strength and its Leadership in Edge Learning
- DCD-SEMI accelerates AES security with the latest IP Core
- Vidatronic Announces Series of Integrated Power Management Unit (PMU) IP Cores Optimized for Augmented/Virtual Reality Applications
- VESA Publishes DisplayPort 2.0 Video Standard Enabling Support for Beyond-8K Resolutions, Higher Refresh Rates for 4K/HDR and Virtual Reality Applications
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |