Avery Design Systems and Rambus Extend Memory Model and PCIe VIP Collaboration
Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration.
Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory controllers including HBM2/2E, GDDR6, LPDDR4, and DDR3/4. Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP. Customers can then license the Avery memory models for use in full SoC verification. Rambus utilizes Avery’s PCIe VIP to verify its PCIe 5.0/4.0 controllers, including Endpoint, Root Port and Retimer modes, and PHYs.
“Avery’s cutting-edge VIP has enabled Rambus to verify controllers which support the most advanced features needed by customers in their current and next-generation designs,” said Brian Daellenbach, senior director of Digital Controllers, IP Cores at Rambus. “The collaboration between Avery and Rambus has helped both companies offer fully-verified IP solutions addressing the latest market requirements.”
“Rambus and Avery are both focused on creating best-in-class, robust, pre-validated memory and PCIe IP solutions which streamline the design and verification process for our customers. We look forward to continuing our collaboration to address the current and next-generation protocols being used by the market,” said Chris Browy, vice president sales/marketing of Avery.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
About Rambus Inc.
Rambus is a provider of industry-leading chips and silicon IP making data faster and safer. With over 30 years of advanced semiconductor experience, we are a pioneer in high-performance memory subsystems that solve the bottleneck between memory and processing for data-intensive systems. Whether in the cloud, at the edge or in your hand, real-time and immersive applications depend on data throughput and integrity. Rambus products and innovations deliver the increased bandwidth, capacity and security required to meet the world’s data needs and drive ever-greater end-user experiences. For more information, visit rambus.com.
|
Avery Design Systems Hot Verification IP
Related News
- Alphawave Semi and InnoLight Extend PCIe over Optics Collaboration with Demonstration of 128Gbps Gen 7.0 over Low Latency Linear Pluggable Optics at ECOC 2024
- Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
- Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs
- Avery Design Systems Pairs PCIe and NVM Express VIP with Teledyne LeCroy Summit Protocol Exercisers
- Rambus, PLDA and Avery Design Announce Comprehensive PCIe 4.0 Solution
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |