Analog Bits to Demonstrate 5nm IP Silicon at TSMC 2021 Online Technology Symposium
Sunnyvale, CA - June 1, 2021 - Analog Bits (www.analogbits.com), a leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be demonstrating Silicon of Foundation IPs including PLLs, Sensors and IO’s, showcasing significant and broad power, performance and area (PPA) benefits of N5 process at TSMC 2021 Online Technology Symposium.
“The Analog Foundation IP is a key differentiator for every high-end SoC that is optimizing for performance, power or density” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Our close collaboration with TSMC gives us the opportunity to help our mutual customers deliver the best possible reliability and quality to the end customers. We truly appreciate our years of strategic partnership with TSMC.”
When: June 1st, 2021
Resources
To learn more about Analog Bits' foundational analog IP, visit www.analogbits.com or email us at info@analogbits.com.
About Analog Bits
Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized Sensors.
With billions of IP cores fabricated in customer silicon, from 0.35-micron to 7-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
|
Related News
- Analog Bits to Demonstrate Working Silicon on TSMC N3E Process at TSMC 2023 North America Technology Symposium
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Analog Bits to Demonstrate Pinless PLL and Sensor IP's in TSMC N5 Process at TSMC 2022 North America Technology Symposium
- Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes
- Analog Bits to Demonstrate Half-Power SERDES at TSMC's San Jose Technology Symposium
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |