English
Plans start for TSMC 2nm fab
By Peter Clarke, eeNews Europe (July 01, 2021)
Taiwan's Ministry of Science and Technology has discussed environmental issues around a proposed expansion of TSMC's Hsinchu operations to house a 2nm wafer fab.
The details of the meeting held online were reported by Taiwan's Commercial Times.
The Hsinchu Science Park Baoshan Land Expansion Project Phase II is considering the environmental impact and mitigation activities for an expansion of Baoshon to provide for expansion of TSMC's 2nm manufacturing capacity.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related News
- TSMC Arizona and U.S. Department of Commerce Announce up to US$6.6 Billion in Proposed CHIPS Act Direct Funding, the Company Plans Third Leading-Edge Fab in Phoenix
- TSMC Plans New Fab for 3nm
- Intel, TSMC to detail 2nm processes at IEDM
- Global Semiconductor Industry Plans to Invest $400 Billion in 300mm Fab Equipment Over Next Three Years, SEMI Reports
- ESMC Breaks Ground on Dresden Fab
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards