Software engineering firm 'obfuscates' Verilog

Software engineering firm 'obfuscates' Verilog
By Richard Goering, EE Times
March 11, 2003 (11:59 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030306S0053

SANTA CRUZ, Calif. — Not many software products are designed to make things more complicated, but an upcoming Verilog "source code obfuscator" from software engineering firm Semantic Designs does just that. Aimed at intellectual property protection, it renders Verilog code unreadable but executable.

The company's core technology, the DMS Software Reengineering Toolkit, is used by customers to create customized utilities, and by Semantic Designs itself to create off-the-shelf tools. Implementations can range from simple utilities that format programs for better readability, to complicated conversion routines t hat can translate a legacy programming language into something more current, like C.

New to Semantic's off-the-shelf lineup is a selection of DMS-based source code obfuscators, which accept a program file and create another that's difficult to reverse engineer. The company currently has PHP, Visual Basic 6, VBScript, and Verilog obfuscators at beta sites, with Java and JavaScript obfuscators in production release.

Although DMS can parse Verilog and VHDL, Semantic doesn't yet have customers doing hardware design. "We are starting to turn our attention to hardware systems, and as DMS is completely agnostic about the languages it processes, our Verilog obfuscator is our first toe in the water," Baxter said.

The "IP problem" makes obfuscation a natural for hardware design, Baxter said. "If I build a component, I may want to give that to you in source form," he said. "But if I do, I might be nervous about you passing it to a third party and claiming it's yours. If I hand you something that's source-co mpatible as far as compilers are concerned, but unreadable by you personally, then I can be more sure about what happens to it."

One way to do that, Baxter said, is to take all the names in the program and replace them with "garbage" names. The compiler will produce the same results, but people won't be able to read and understand the Verilog code.

"The bigger the software is, the more effective this is," Baxter said. "If you want to protect a flip-flop, this is not going to do it, but if you want to protect a microprocessor core, it will work very well."

There's one caution, however. Users should obfuscate the contents of modules, but not the interfaces between modules, Baxter noted. "If the component is going to talk to something else, you have to agree on signal names," he said. "So you can give the obfuscator a list of signals you don't want it to touch, like external busses, clocks, and feedbacks."

Baxter said that an IEEE 1364 Verilog obfuscator should be in production release in about a month, and that the company may later roll out a VHDL obfuscator. And Semantic Design is thinking about other hardware applications for DMS. Baxter noted that this core technology processES multiple languages, such as C and Verilog, at the same time.

"If co-design is ever to become mainstream, it must process all the languages used to describe and implement the system," Baxter said. "DMS can do it. We know of no other tool on the planet that can do this. And so we expect to make a big splash in the co-design world, when we're ready."