DDR5 Ecosystem Ramps Up
By Gary Hilson, EETimes (November 1, 2021)
Like all iterations of DRAM, DDR5 will need an ecosystem of supporting technologies for it to become dominant, even as advanced workloads drive memory bandwidth requirements.
Rambus Incorporated is already laying the groundwork for DDR5 implementations more than a year away. The company recently announced it is sampling its 5600 MT/s 2nd-generation DDR5 registering clock drivers (RCD) to the major DDR5 memory module (RDIMM) suppliers. John Eble, vice president of product marketing for memory interface chips, said it will be several years before systems will be hitting the market. However, supporting technologies such as its RCD need to be evaluated and qualified by customers now so the ecosystem is ready to provide the bandwidth and capacity that will be required in next-generation data centers.
A DDR5 RCD along with data buffers (DB) are used in DDR5 Registered DIMMs (RDIMMs) and DDR5 Load Reduced DIMMs (LRDIMMs) to deliver higher bandwidth, performance, and capacity when compared to unbuffered DIMMs. RDIMMS, and LRDIMMs to reduce load on the CPU and improve the signal integrity of the command/address bus. The role of the RCD is as a key control plane chip which distributes Command/Address signals and clock to the DRAM devices on the DIMM. Rambus’ RCD can support DDR5 LRDIMMs when paired with 10n DB chips per module and reduces the effective load on the data bus to enable higher-capacity DRAMs on the module without reducing latency.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related News
- Rambus Expands Industry-Leading Memory Interface Chip Offering to High-Performance PCs with DDR5 Client Clock Driver
- Rambus Expands Chipset for Advanced Data Center Memory Modules with DDR5 Server PMICs
- Rambus Advances Data Center Server Performance with Industry-First Gen4 DDR5 RCD
- Rambus Delivers 6400 MT/s DDR5 Registering Clock Driver to Advance Server Memory Performance
- Rambus Expands Portfolio of DDR5 Memory Interface Chips for Data Centers and PCs
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset