USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores with Superfast speed and High-power efficiency for lag-less data processing is Silicon Proven and available in 8nm LPP for licensing

29^th November 21 – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP Cores in 8nm LPP process node which is silicon proven in major Fabs and in mass production with full certification, greatly increased power efficiency and decreased logic area compared to higher nodes.

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP Cores consist of Universal Serial Bus (USB) compliant with the USB 3.0 (USB High-speed and Full speed), Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, and Serial ATA (SATA) compliant with SATA 3.0 Specification. Due to the architecture of the 8nm LPP process node, lower power consumption is achieved along with support of additional PLL control and reference clock control. The high level of control allowed in the PHY also makes the Combo PHY reliable and effective in different power consumption levels.

Compatible with PCIe2/USB3/SATA3 base Specification and fully compatible with PIPE3.1 interface specification the USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP Cores can achieve a data rate configurable to 1.25G/1.5G/2.5G/3G/5G/6G for different application. It supports 16-bit or 32-bit parallel interface when encode/decode enabled and 20-bit parallel interface when encode/decode is bypassed. Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm makes it flexible along with programmable transmit amplitude.

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP cores in 8LPP has PCIe Mode that supports 100MHz differential reference clock input or output (optional with SSC) and Beacon signal generation and detection. USB3.0 Mode supports Low Frequency Periodic Signalling (LFPS) generation and detection. SATA Mode supports COMWAKE, COMINIT and COMRESET (OOB) generation and detection along with RX low latency mode. These with added benefit of process node allows L1 sub-state power management.

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP cores have been used in semiconductor industry’s Cellular Electronics, PC, Data storage (SSDs), Multimedia Devices, Servers, Cryptocurrency and other Consumer Electronics …

In addition to USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores, T2M ‘s broad silicon Interface IP Cores Portfolio includes Standalone USB, PCIe, Serial ATA and also HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 5nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com

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