Graphcore Supercharges IPU with Wafer-on-Wafer
By Sally Ward-Foxton, EETimes (March 3, 2022)
Graphcore unveiled its third-generation intelligence processing unit (IPU), the first processor to be built using 3D wafer-on-wafer (WoW) technology.
Codenamed the Bow IPU, Graphcore’s new AI processor achieves up to 40% higher performance and 16% better power efficiency than the previous (non-WoW, but otherwise identical) product, launched in 2020.
“Wafer-on-wafer technology sets a direction in terms of where Graphcore is heading,” said Graphcore CEO Nigel Toon. “We’ve been working very closely with TSMC on this technology, developing this over the last two years. We’ve been in extensive production qualification over the last year with very detailed testing for reliability, and we’re now at the stage where this technology is ready for full volume production.”
Graphcore plans to drastically increase its price/performance metrics by offering the new parts at the same price as the old ones. Customers can swap over to Bow IPUs without making any software changes, the company said.
Graphcore also announced that it will use future generations of WoW IPU to build a product it calls the Good Computer, an ultra-intelligence AI supercomputer product capable of 10 ExaFLOPS, in response to customer demand.
E-mail This Article | Printer-Friendly Page |
|
Related News
- Synopsys VCS Used by Graphcore to Verify Next-Generation Colossus GC200 IPU
- Mentor enhances tool portfolio for TSMC 5nm FinFET and 7nm FinFET Plus processes and Wafer-on-Wafer stacking technology
- Graphcore joins SoftBank Group to build next generation of AI compute
- Is Graphcore Deal Finally About to Close?
- Softbank reported to be in talks to buy Graphcore
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity