Xylon Demonstrates Hot Swapping of Programmable FPGA/SoC Chip Parts
March 17, 2022 -- Xylon is proud to present a new addition to its reference design portfolio - the Dynamic Function eXchange Design Framework with Isolation Design Flow, or logiREF-DFX-IDF for short. The logiREF-DFX-IDF Design Framework is prepared for use with Xylon's logiVID-ZU-GMSL2 kit. The design is fully prepared for the new Xilinx Vitis Unified Software Platform 2021.1 and Xilinx Vivado® Design Suite 2021.1.
The design framework is intended to build upon our existing logiADAK-VDF-ZU design by incorporating multiple new features to showcase their advantages and new opportunities they open up for developers. The basis of the design is the Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation board that processes four HD video streams from four Maxim Integrated GMSL2 video interface automotive cameras. Each camera is reconfigurable on the fly with three different filters, on the programmable logic level due to the use of Dynamic Function eXchange (DFX).
DFX is the ability to reconfigure blocks of programmable logic while they are continually operating, with the use of partial bit files. DFX is working in tandem with the used Isolation Design Flow (IDF) methodology, which isolates potential faults to a single region on the chip, to ensure functional safety for safety-critical applications.
Another layer in this drive towards functional safety is the implementation of the Soft Error Mitigation (SEM) IP Core in the design. SEM provides the ability to detect and correct single errors in the configuration memory of the programmable logic, as well as detection of multiple configuration errors, in which case it triggers reconfiguration for the affected isolated chip region. A demo application of error correction is included in the design framework.
The logiREF-DFX-IDF reference design, including the Xylon IP Cores, is available for a free evaluation to all registered users on Xylon's website: https://www.logicbricks.com/logicBRICKS/Reference-logicBRICKS-Design/Xylon-Reference-Designs-Navigation-Page.aspx .
For the datasheet, please refer to the following link: https://www.logicbricks.com/Documentation/Datasheets/IP/logiREF-DFX-IDF_hds.pdf .
Xylon offers design services, consultations and other forms of support for any developer looking to implement DFX or IDF into their products. For more information regarding this, please contact Xylon at info@logicbricks.com .
|
Xylon Hot IP
Related News
- Xylon Announces New logicBRICKS Vision AI Framework for AMD Adaptive SoCs
- Altera Demonstrates its Comprehensive FPGA, SoC and Power Solutions at APEC 2015 Offering Greater Efficiencies in Electronic Design
- Microsemi Steps Up Its Cyber Security Leadership in FPGAs: SmartFusion2 SoC FPGAs and IGLOO2 FPGAs Enhanced with Physically Unclonable Function Technology
- Xylon Announces A Real-Time Low Latency Video Rotation Reference Design for Xilinx Zynq-7000 All Programmable SoC
- Xylon Showcases the World's Fastest 3D Graphics Engine for Xilinx Zynq-7000 All Programmable SoC
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |