Electronic Design Services Experts Launch Integre Technologies
Company Augments ASIC and FPGA Design Teams, Provides Full Turn Key Design Services, Offers Mixed Signal Design Services
ROCHESTER, New York-- March 24,2003--Mark Blejwas and Fred Rakvica, Managing Partners of Integre Technologies, based here, announced that Integre was formed to offer digital and analog design services to electronic design service customers across North America.
Integre Technologies, staffed with seasoned Electrical Engineering consultants with decades of experience, is focused on assisting customers across a broad array of needs that address the ASIC and FPGA flows. The company's design service teams are experienced with verifying and designing silicon circuits and systems of up to 5 million plus gates, comprised of both mixed signal and digital components for applications such as wireless, embedded and RF.
"We saw the downturn in the economy as an opportunity to start an electronic design services company, remarkedFred Rakvica, Integre's co-founder and managing partner. "We are growing our company now, and preparing to take advantage of the upturn."
"The marketplace has forced efficiency in the ASIC flow. In the long run we see this as a plus for our business. Our services are designed to allow companies to maintain a high level of efficiency by providing top quality results in a timely manner," added Mark Blejwas, co-founder and managing partner of Integre Technologies.
Integre's Vision and Focus
Integre believes that high-end verification of large complex designs is a discipline whose need will continue to grow due to the increased pressure for first silicon success.
The company also focuses on the high end FPGA market and mixed signal designs for embedded systems, especially in the wireless arena and sees growing opportunities in the mixed signal market.
Blejwas noted, "The typical separation of digital and analog efforts is disappearing. Our expertise in both digital and analog flows allows us to assist customers in this transition."
About Integre's Managing Partners and Co-Founders
Fred Rakvica and Mark Blejwas, Managing Partners and Co-Founders of Integre, are experienced design team managers.
Fred Rakvica has successfully managed a profitable center of engineers for the last five years, and has over 20 years of experience in the field of design, from ASICs and FPGAs to circuit boards and embedded software. He holds a BSEE degree from Clarkson University and an MSEE from the Rochester Institute of Technology.
Mark Blejwas' experience is with the entire ASIC and FPGA flow, including circuit board design, embedded software, test fixtures and manufacturing support in a product development environment. He holds a BSEE degree from Lafayette College and a Masters of Engineering degree from Rensselaer Polytechnic Institute and is a licensed Professional Engineer in the state of New York
About Integre
Integre Technologies, founded in September 2002, is an electronic design services company providing short- and long-term system and integrated circuit design support. With decades of experience, Integre's electronic engineers assist electronic manufacturers in maintaining schedule, budget, and quality goals by providing immediate expertise targeting a variety of electronic engineering needs.
Integre's headquarters are at 3495 Winton Place, Suite E295, Rochester, New York 14623
To find out more about Integre Technologies call (585) 292-1770 or visit: www.integretek.com
-end-
Note to Editors: All trademarks and tradenames are the property of their respective owners.
Related News
- Cadence Collaborates with Amazon Web Services to Deliver Electronic Systems and Semiconductor Design for the Cloud
- Xilinx and Barco Silex Ease Video Over IP Development With Launch of All Programmable Solutions and Design Services at IBC 2012
- Altera Accelerates Customer Design Productivity and Innovation With Launch of Design Services Network Program
- CEVA Speeds Customer's Time To Silicon With The Launch Of CEVA Services
- Commercial launch of the 3G Patent Platform services to limit maximum royalties for 3G systems
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
E-mail This Article | Printer-Friendly Page |