English
Chiplets Get a Formal Standard with UCIe 1.0
Recent uptick in chiplet interest has led to concerns about lack of best practices
By Gary Hilson, EETimes (April 8, 2022)
The recently announced Universal Chiplet Interconnect Express (UCIe) 1.0 specification covers the die–to–die I/O physical layer, die–to–die protocols, and a software stack model leveraging PCI Express (PCIe) and Compute Express Link (CXL) industry standards.
It’s fair to say that UCIe is a long time coming. Chiplets aren’t new, but recent uptick in interest in the technology has raised concerns about the need for a formal standard and best practices.
UCIe has garnered a lot of interest in recent years because of its tried–and–true nature and its ability to help semiconductor companies solve common problems faced today. Chiplets offer an approach to semiconductor design and integration that hold the promise of speeding things up with Moore’s Law, which is now nearly six decades old. The pace of semiconductor manufacturing advancement has also been waning as of late.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Accellera's Security Annotation for Electronic Design Integration Standard 1.0 Moves Toward IEEE Standardization
- Khronos Releases Vulkan SC 1.0 Open Standard for Safety-Critical Accelerated Graphics and Compute
- SystemC Ecosystem gets boost with Accellera's new SystemC CCI 1.0 Standard
- Khronos Group Releases NNEF 1.0 Standard for Neural Network Exchange
- OSCI Welcomes Adoption of SystemC AMS 1.0 Standard Inside Industrial Design Flows for Mixed-Signal System Design
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity