Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol

Avery to offer VIP, verification aids to enable design with recently-announced die-to-die interface standard backed by industry leaders

Tewksbury, MA – June 15, 2022 – Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage the recently-introduced standard for die-to-die interface connectivity. Avery’s offering includes high-quality models and test suites that support pre-silicon verification of systems using UCIe.

As part of the support for the standard, Avery has joined the UCIe consortium which administers the specification, and includes founding members: Intel, AMD, Arm, Qualcomm, TSMC, Samsung, ASE, Google, Microsoft and Meta.

UCIe was announced earlier this year as a mean to provide interoperability of chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. The focus of the initial specification (Version 1.0) covers the UCIe Adapter and PHY including die-to-die I/O physical layer, Die-to-Die protocols, and software stack which leverage the well-established PCI Express® (PCIe®) and Compute Express Link™ (CXL™) industry standards in addition to a protocol-agnostic raw transfer mode.

“As the use of various packaging methods evolves and grows, we are excited to be involved at the ground floor of this important new standard for enabling a more open, interoperable ecosystem for chiplet design. Much the way Avery has helped provide comprehensive verification IP solutions for SoC and IP companies, we believe giving engineers early access to reliable verification models and testsuites will help accelerate its use and be an important factor in realizing the vision of PCIe and CXL based chiplets based on UCIe and supporting its evolution,” said Luis E. Rodriguez, verification solutions architect at Avery.

“A key to success for any standard is a broad and robust ecosystem. Avery’s experience in enabling the adoption of open standards like CXL and PCIe demonstrates commitment to delivering timely, accurate design and verification tools to help meet the market requirements. We look forward to their participation in the adoption of UCIe to make chiplet interoperability a reality,” said UCIe Chairman and Intel Senior Fellow Dr. Debendra Das Sharma.

Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its UCIe offering supports standalone UCIe die to die adapter and LogPHY verification along with integrated PCIe and CXL VIP to run over the UCIe stack. In addition to UCIe models it provides comprehensive protocol checkers, coverage, reference testbenches, and compliance test-suites utilizing a flexible and open architecture.

Figure 1: UCIe to enable an Open Chiplet Ecosystem delivering Platform on a Package

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, UCIe, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

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