DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
World's First AV1 Decoder Silicon IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
June 20, 2022 -- Allegro DVT, the leading provider of video processing silicon IPs and video compliance streams, has announced that its D310 AV1 decoder silicon IP now supports 12-bit sample size and 4:4:4 chroma sub-sampling. Emerging applications such as cloud-gaming, automotive and screen mirroring will directedly benefit from these new features to provide a superior video quality and preserve the finest details in video content.
Allegro DVT’s D310 IP is part of the D3xx highly customizable silicon IP family that builds on a scalable architecture allowing picture resolutions ranging from to HD, 4K and up to 8K/16K while providing support for sample sizes from 8-bit to 12-bit and chroma subsampling from 4:0:0 up to 4:4:4.
Allegro DVT is able to address the growing demand of state-of-the-art video processing blocks in advanced System-on-Chips (SoCs) by providing highly configurable decoding IP core supporting a variety of selectable codecs. In addition to AV1, the D3x0 family also supports JPEG, H.264, HEVC, VP9 and VVC video formats. Furthermore, Allegro DVT’s unique and scalable architecture approach offers the best trade-off between silicon size and power consumption and keeps the operating frequency of the resulting 8K solutions at a reasonable level to allow physical implementations in mainsteam and cost-efficient process node technologies.
The D310 is immediately available with a comprehensive documentation and SW drivers for a smooth integration into video SOCs.
Nouar Hamze, CEO of Allegro DVT commented “Allegro DVT is committed to supporting the AV1 ecosystem and accelerating the adoption of this promising video codec. Our D310 product is the very first AV1 decoder IP to provide support for 12-bit pixel size and 4:4:4 chroma subsampling format. These high-end features will extend the breadth of target applications to includes advanced HDR, cloud-gaming, wireless display and automotive in which preserving video quality is of utmost importance. This IP represents the culmination of our engineering and marketing effort in bringing together the requirements of vastly different applications and generating solutions that are optimal in terms of power, performance, and area for our end customers.”
For more information, contact us.
|
Allegro DVT Hot IP
Related News
- Allegro DVT Releases New Versions of its Encoder and Decoder IPs with Support for 12-bit sample size and 4:4:4 Chroma Format
- Allegro DVT Adds Support of 4:2:2 10-bit Video Profiles to its Multi-Format Encoder/Decoder Hardware IPs.
- Allegro DVT improves its HEVC Decoder silicon IP with 10 bit support
- Allegro DVT Announces the Industry's First MPEG-5 LCEVC Decoder Silicon IP
- Allegro DVT Launches the World's First Hardware-Based VVC/H.266 Decoder Silicon IP
Breaking News
- Axelera AI Secures up to €61.6 Million Grant to Develop Scalable AI Chiplet for High-Performance Computing
- Baya Systems Revolutionizes AI Scale-Up and Scale-Out with NeuraScale™ Fabric
- Europe takes a major step towards digital autonomy in supercomputing and AI with the launch of DARE project
- Infineon brings RISC-V to the automotive industry and is first to announce an automotive RISC-V microcontroller family
- EnSilica Secures €2.13 Million European Space Agency Development Contract
Most Popular
- MosChip® Launches MosChip DigitalSky GenAIoT™ to Accelerate the Development of Next-Gen Connected, Intelligent Products
- Arm vs. Qualcomm: The Legal Tussle Continues
- indie Semiconductor and GlobalFoundries Announce Strategic Collaboration to Accelerate Automotive Radar Adoption
- Silvaco Expands Product Offering with Acquisition of Cadence's Process Proximity Compensation Product Line
- Marvell Demonstrates Industry's Leading 2nm Silicon for Accelerated Infrastructure
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |