TSMC Creates Design Options for New 3nm Node
By Alan Patterson, EETimes (June 22, 2022)
Taiwan Semiconductor Manufacturing Co. (TSMC) has created versions of its upcoming 3nm FinFET node that’s ramping up later this year, allowing chip designers to enhance performance, power efficiency, and transistor density — or select a balance of those options.
TSMC’s 3nm technology, starting production later in 2022, will feature the company’s FinFlex architecture offering choices of standard cells with a 3–2 fin configuration for performance, a 2–1 fin configuration for power efficiency and transistor density, or a 2–2 fin configuration for efficient performance.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related News
- TSMC Expansion in Arizona to Target 3-nm Node
- OpenAI to tape-out on TSMC 3nm this year
- Unveiling the Availability of Industry's First Silicon-Proven 3nm, 24Gbps UCIe™ IP Subsystem with TSMC CoWoS® Technology
- Alphawave Semi Launches Industry's First 3nm UCIe IP with TSMC CoWoS Packaging
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset