English
Meet Axiomise's Ashish Darbari at DAC to Learn about Benefits of Formal Verification
Will Present “Taming the Beast: RISC-V Formal Verification Made Easy”;
Panelist on “Those Darn Bugs! When Will They be Exterminated for Good?”
LONDON –– June 28, 2022 ––
WHO: Dr. Ashish Darbari, CEO and founder of Axiomise, the leading provider of cutting-edge formal verification services and custom solutions
WHAT: Will be a visible presence at this year’s Design Automation Conference (DAC) promoting the adoption of Formal Verification.
He will serve as a panelist on “Those Darn Bugs! When Will They be Exterminated for Good?” moderated by Brian Bailey of Semiconductor Engineering Monday, July 11, from 3 p.m. until 3:45 p.m. at the DAC Pavilion (second floor).
Dr. Darbari will present “Taming the Beast: RISC-V Formal Verification Made Easy” at the Cadence Design Systems Theater (DAC Booth #1511) Monday at 4 p.m. and Tuesday at 1:30 p.m.
WHEN: DAC runs from Monday, July 11, through Wednesday, July 13, from 10 a.m. until 6 p.m. at the Moscone West in San Francisco. Registration is open.
It will be collocated with SEMICON West 2022 Hybrid at the Moscone Center. Registration is open.
About Axiomise
Axiomise is dedicated to furthering the adoption of formal verification through its unique combination of consulting, services and specialized verification solutions for RISC-V. Founded by Dr. Ashish Darbari, a formal verification practitioner for over two decades, it offers cutting-edge, formal verification training, consulting and services. An active user of all formal technologies, including theorem proving, model checking and equivalence checking, Dr. Darbari and his team have trained more than 200 engineers across the semiconductor industry. Dr. Darbari has 46 patents in the field of formal verification.
|
||||||
Related News
- Axiomise launches Essential Introduction to Practical Formal Verification Training
- Axiomise Showcases Value of Formal Verification at DVCon Japan and DVCon India
- Axiomise Accelerates Formal Verification Adoption Across the Industry
- The Art of Predictability : How Axiomise is Making Formal Verification Mainstream
- Axiomise Unveils Intelligent Debug Solution for Formal Verification of RISC-V Cores
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |