Innolink - The advanced Chiplet solution complies with the Universal Chiplet Interconnect Express (UCIe) standard

July 7, 2022 -- In March 2022, chipmakers Intel, TSMC, and Samsung joined forces with ten industry giants including ASE Group, AMD, ARM, Qualcomm, Google, Microsoft, and Meta (Facebook) to launch UCle standard, a new Universal Chiplet Interconnect Express standard. In the same breath, Innosilicon, a domestic IP provider, ASIC design house, and GPU-enabled leader, announced the first homegrown development of Chiplet solution compatible with the UCIe standard IP solution - Innolink™ Chiplet, which is the first cross-process, cross-package Chiplet connectivity solution, and has been successfully verified in mass production on advanced processes.

▲ Innolink™ Chiplet Interconnection Overview

The demand for computing power, memory bandwidth, and storage capacity continue to grow due to the rising demand for high-performance computing, cloud computing, edge computing, IoT, 5G, AI, autonomous driving, and portable and wearable devices. The advanced process technologies are reaching their limit due to the dilemma of the long product fabrication cycle, high engineering cost, and low yield. In addition, the application of chips is getting more and more diversified, and the demand for power consumption and heat dissipation of chips is increasing. In this case, the chip design companies illustrate that when following the traditional way of having an entire chip manufactured in one single process, the development of the technology, cost, and yield are all contradictory factors. The Chiplet technology is rapidly being developed to solve this issue.

▲ Dramatic increases in development costs have been caused by increased transistor density and advanced process development.

Chiplets allow designers to create densely and power-efficient interconnects between processor cores, mixed-signal modules, memory and other device components. Chiplet technology is a different way of integrating multiple dies in a package or system. The multi-core (Die to Die) interconnection assembles Chiplets in a package and connects them using a die-to-die interconnect scheme. The use of shorter distance, lower power consumption, higher density chip bare die connection, breakthrough single chip (monolithic) performance, and yield bottleneck, reduce the development time, cost, and risk of larger chips, to achieve the integration of heterogeneous complex high-performance SoC, to meet the dies of different manufacturers.

▲ Multiple-core interconnection is what chiplet technology is all about.

Each company's own proprietorial standards were diverging from Chiplet's early development protocols.

In recent years, the tier one fabless Semiconductor companies and system houses, such as AMD, Apple, and Nvidia, have launched a number of Chiplet products and have achieved great success in various applications, further proving the feasibility and development prospects of Chipletization in the market.

Chip manufacturers were pushing their own proprietary standards which were not interoperable when they began designing and building Chiplet products. For example, Marvell's Kandou bus interface when launched its modular chip architecture, while NVIDIA had a high-speed interconnect NV Link solution for GPUs. Intel defined its EMIB (Embedded Die interconnect bridge) interface. TSMC and AARM cooperated on LIPINCON interconnect protocol. AMD also used their Infinity Fabrie bus interconnect technology and so on. Innosilicon was not far behind in delineating the Innolink™ Chiplet proprietary standard and achieving volume production in 2020.

Chiplets provide the path to integrate IP blocks that serve various functions and then package them according to an application. It enables the merging of multiple dies' computing power under large bandwidth to form a diverse and multi-process integrated circuit vessel. Apparently, if each Chip manufacturer were creating its own standard, this will lead to interconnection barriers between Chiplets from different vendors and limit the future development of Chiplet ecosystem. Therefore, to achieve high-speed interconnection between each Chiplet, it is necessary for chip design companies, EDA vendors, Foundries, packaging houses, and others in semiconductor industry chains to coordinate and establish a unified interface standard, so as to lay the foundation for the future development of Chiplet ecosystem in order to really reduce costs, and accelerate the development. Thus, the UCIe standard was born.

▲ Heterogeneous systems can be achieved with Chiplet technology with multiple cores.

▲ Apple's M1 Ultra chip applies Chiplet technology to double performance

The establishment of UCIe gives a strong impetus to the development of Chiplet connectivity standards.

The release of the UCIe standard has attracted much attention and discussion in the industry because it is a significant step forward in defining a common interconnect protocol for interoperability. This standard has been defined to be applicable to all types of Chiplet packaging technologies including wafer-level, package-on-package, and multi-chip module technologies. The UCIe has been built from the ground up with semiconductor industry participation and developed under the joint stewardship of leading semiconductor technology companies. Their main goal is to break through the Chiplet interconnect challenge, reduce the cost, and improve performance.

The Universal Chiplet Interconnect Express (UCIe) is an open specification that defines the interconnect between Chiplets within a package, enabling an open Chiplet community.

AMD, ARM, Advanced Semiconductor Engineering, Inc. (ASE), Google Cloud, Intel Corporation, Meta, Microsoft, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing Company are dedicated to this open industry standard organization to promote and further develop the technology, and to establish a global ecosystem supporting Chiplet design. It enables package-level interconnection between Chiplets with high bandwidth, low latency, low cost, low power consumption, etc. It can meet the insanely high demand for computing power, memory, storage, and interconnection in intensive high-computing applications including cloud, edge, enterprise, 5G, automotive, high-performance computing and mobile devices, etc. The ability to package and integrate different dies, which can come from different foundries or can be designed and packaged in different ways, is allowed by the UCIe standard.

Innolink™ Chiplet Solution Overview

▲ Mr. Zachary Gao, Innosilicon Chiplet Architect, presenting Innolink™ Chiplet Solution at ASIC Design Ecosystem Conference

Just two weeks after the official release of the UCle standard, the Innolink™ Chiplet was announced by Innosilicon as the first in-house developed interconnect PHY which is fully compliant with UCIe standard. It is because Innosilicon was in a pioneering role and started our research and development of the DDR-like Chiplet technology two years ago. At the Design Reuse Global Conference in 2020, Innosilicon first revealed Innolink A/B/C products to the industry. Innosilicon Chiplet Architect said: Innosilicon in the Chiplet technology field has accumulated a lot of experience from closely working, communicating, and exploring the requirements with TSMC, Intel, Samsung, Micron, and other industry leaders.

Innosilicon is proud that we have done due diligence and predicted what interconnect protocols will be used by the industry. The end result is that we are delivering our Innolink™ which is consistent with the UCIe standard and is the first world-leading independent UCIe Chiplet solution.

▲ Innolink A/B/C implementation

Innolink™ Chiplet, a forward-thinking innovative technology for the Interconnection solution

SerDes technology is used by companies in the Semiconductor industry because they believe that the cross-process and cross-package nature of Chiplet will expose them to complex signal paths. According to Innosilicon's extensive research of various Chiplet applications, technologies, and trends, we believe that Chiplet will be much better applied if it's interfaced with DDR-like protocol and that different packaging types require the use of differential DDR technology solutions.

The route from Die to Die, to the die interconnect, to the interposer, and to the package is very short. The signal integrity is very good. The use of DDR-like technology in Chiplet application to optimize the power efficiency with high bandwidth throughput is more beneficial according to the conclusion of Innoslicon.

Not to mention, the Chiplet technology enables the device to achieve high bandwidth and low power. DDR technology meets the comprehensive requirements of high density, low power, and low latency of multi-die interconnection, which makes multiple dies work as a single die and extends the single interconnect bus to dies. By considering all the aforementioned factors, Innosilicon adopted DDR-like protocols in Innolink-B/C PHY development to provide a high-speed, high-density, and high-bandwidth interconnection solution based on GDDR6/LPDDR5 technology.

A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits or Chiplet, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate. MCM is cost-effective and is the first choice for Chiplet applications. On the other hand, the advanced package such as Interposer, with high density, low yield rate, high cost, is another option for high-performance applications that are not price sensitive. Before the official release of UCIe specification, Innosilicon has made the benchmark of the MCM vs Interposer technologies in the early feasibility study stage of Innolink-B/C products and verified its accurate judgment of the market prospect and Chiplet technology trend.

▲UCIe defines the key performance indicators for different packaging standards

For lengthy trace routing on PCB or cable, Innolink-A technology provides SerDes differential signal-based connection solution to compensate for the signal attenuation of a long trace. The differential signaling is more immune to noise and distortion so that the signals are less affected by impedance mismatch. SerDes differential signaling also requires less power than single-ended signaling. With the power savings, the signal integrity of differential signaling can be enhanced.

Innolink-A/B/C family product enables cross-process, cross-package Chiplet mass production solutions, making Inosilicon the industry leader in the Chiplet world. In addition to Innolink™ Chiplet IP offering, Innosilicon also provides package design, reliability/qualification service, signal integrity analysis, DFT insertion, thermal simulation, and test vector generation to form a complete Chiplet solution.

▲ Innolink™ Chiplet design incorporates advanced UCIe's Chiplet connection standard across different packaging types

The figure illustrates that UCIe is divided into 3 layers, Protocol Layer, die-to-die Adapter interconnection layer, and Physical Layer. Among them, the protocol layer is the commonly used PCIE, CXL, and other upper-layer protocols, the bottom Die to Die and PHY physical layer, that is, and Innolink™ the same structure of implementation is adopted.

In summary, Innosilicon's rich high-speed design experience, combined with its strong heritage knowledge, including SerDes, GDDR6/6X, LPDDR5/DDR5, HBM3, substrate, interposer, signal integrity, advanced process packaging, and proven through a large number of tier-one customers in volume production. This is undeniably the outcome of the long-term R&D investment and dedication of skilled talents at Innosilicon. Innosilicon accurately modernized the direction of Chiplet technology and completed the design verification with foresight, which is consistent with the later deployed UCIe technology specifications, laying the foundation for Innolink™ to be compatible with UCIe standard and become the industry-leading solution.

Innolink™ Chiplet ammunition is maturely available for customers who want to build UCIe products

The Innolink™ Chiplet represents the marriage of Innosilicon’s leading high-speed interconnect IP with our advanced semiconductor manufacturing technologies. Next, we'll talk about what role technology, our experience, and work contribution are involved but not limited to.

▲ 18Gbps GDDR6 Single-Ended Eye validated from volume production

▲ 21Gbps PAM4 DQ Eye, single-ended

▲ HBM3 6.4Gbps high-speed eye diagram

▲ World's first GDDR6/6X combo ASIC product shipped in volume

▲ 32/56G SerDes Eye Diagram

▲ Innosilicon Fantasy-1, an 4K High-Performance GPU adopting Innolink™ Chiplet technology with a 2x performance boost.

▲ Signal Integrity Analysis for the advanced package

▲ Thermal Simulation at the Package level

Realizing those roles of technology, experience, and work contribution to the step-to-step high-speed products accomplishments made by Innosilicon, we all know that Rome is not built in a single day. There isn't a shortcut or magic here. Innosilicon's technology team is always on the move, seeking the best solutions and solutions to the latest Chiplet trend and problems. Innosilicon technology team is always committed to innovation and to continuous improvement. We are always ready to take on new challenges and opportunities. This makes Innosilicon have the confidence and experience to create and manufacture high-end semiconductor IP in the semiconductor industry.

Great leadership

The CEO of Innosilicon, Mr. Gordon Ao, comes from a technical background and knows how to motivate the entire team. Gordon always encourages everyone to think outside the box and come up with innovative ideas. He is dedicated himself leading the mixed-signal design group and is in charge of top-level architecture design, micro-level circuit design, area, and power optimization. Gordon believes that the Innosilicon's success lies in the dedication and commitment of the team. There is no room for error. He also believes that the success of Innosilicon relies on innovation, creativity, the keen judgment of the market, and continuous lead in technology development. With all the dedication and contribution, It is not surprising that Innosilicon R&D team can continue to overcome the technical challenges and has created hundreds of advanced intellectual properties that Innosilicon is uniquely positioned to provide.

Gordon believes that the demand for the advanced process of high-performance application-specific integrated circuits is growing at an exponential rate. The demand is driven by a variety of high-speed applications, where smaller and more powerful integrated circuits are required to meet consumer expectations. The demands of these applications are driving the evolution of the semiconductor industry in ways that Gordon has not seen before. Based on its dynamic landscape, Gordon oversees the importance of Chiplet technology and believes that the future of advanced technology lies in the use of Chiplet technology, a technology that he is convinced will be adopted within the next decade.

▲ The CEO is personally involved in the product research and development work, leading the team to strive for leadership!

▲ Mr. Gordon Ao, CEO of Innosilicon, was presenting in China IP and ASIC design Ecosystem conference

The Importance of quality IP availability in FinFet technology nodes

Delivering an advanced quality IP is a complicated process, from digital to analog, front-end/back-end design implementation to product tape out, to the package and testing, to the IP validation and yield improvement required by all seasoned professionals. With its 16 years of design and manufacturing experience, Innosilicon has chartered a core competence team and its products are being widely used in various high-speed applications by well-known industrial leaders. Innosilicon, a latecomer to the IP industry has been making tremendous progress in the last couple of years and gained a sizable high-speed IP market share.

Innosilicon has also gained industry recognition for being a valuable partner to multiple foundries. We are able to get substantial support from our foundry partners in terms of process, cost, and capacity. Together, these benefits come together to stronger Innosilicon because we take a frontier role in FinFet IP development.

As the world continues to shift toward a more high-performance computing decade, the importance of advanced IP technology processes such as FinFets technology is expected to rise. A visionary customer looks forward to 3 to 7 years of their product cycle and the same product strategy is agreed upon by Innosilicon. Therefore, Innosilicon wants to drive the market instead of the market driving us. The emerging-market can be served and prolong the product life cycle with the availability of FinFet intellectual property offered by Innosilicon.

▲ 2021 IP and ASIC Design Ecosystem Conference sponsored and hosted by Innosilicon

Innosilicon provides leading-edge solutions for customers seeking cost, size, and power reduction while improving performance and reducing their time to market. In the past 16 years, Innosilicon achieves our customer’s goals through the design, development, and silicon verified IP (intellectual property), production of SoC (System on Chip) solutions, ASIC (Application Specific Integrated Circuits) in various field domains such as high-performance computing, multi-media terminals, automotive electronics platforms, IoT platforms, etc. Innosilicon has been acknowledged by the industry for its innovative IP solutions and has taped out over 200 successful designs, developed over 1000 silicon verified IP (intellectual property) blocks, over 6 billion devices with our embedded intellectual properties, and over 1 billion high-end custom ASICs.