Introducing PCIe 4.0 PHY IP Cores in 7nm for a reliable, Low area and High-Speed Interface Peripheral slot for all your High-End Devices
October 10, 2022. – T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s PCI-SIG compliant PCIe 4.0 PHY IP Cores Silicon Proven in 7nm process technology with matching PCIe 4.0 Controller IP cores. This PCIe Cores have been in use in several different chipsets and applications.
The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design. A full variety of PCIe 4.0 Base applications are supported by the PCIe 4.0 IP cores, which also complies with the PIPE 4.4.1 specification. The IP cores integrates high-speed mixed signal circuits to support PCIe 4.0 traffic at 16Gbps. This Silicon Proven 7nm technology boasts a Low power consumption, achieved due to support of additional PLL control, reference clock control, embedded power gating control and support for all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 spec.
The PCIe 4.0 SerDes PHY IP cores supports data transfer rates of 16Gbps and is backward compatible with data rates of 2.5Gbps, 5.0Gbps, and 8.0Gbps for PCIe 3.1, PCIe 2.1, and PCIe 1.1, respectively. The PCIe 4.0 IP cores may satisfy the needs for various channel circumstances since it supports both TX and RX equalisation method along with a x4 width physical lane which can also support x1, x2, x4, x8, x16 lane configurations with bifurcation. Parallel interface of 32-bit is supported with an input reference clock of 100 MHz. It can also support parallel interface data clock of 62.5 MHz, 125 MHz and 250 MHz and 500MHz.
The PCIe 4.0 Controller IP cores presents a programmable, flexible AMBA AXI connection interface to the user and may be configured to support endpoint, root port, and dual-mode topologies, allowing for a range of use cases. For extremely high performance, it has a 512b Controller architecture and 64B PIPE interface. AXI4/Native Interfaces and a highly programmable, reliable DMA architecture guarantee a versatile user interface and an effective gate controller.
As the industry standard for PCI Express, PCIe 4.0 PHY IP Cores in 7nm which T2M offers is in volume production and has been successfully implemented in a wide range of applications such as SSD Controller, Digital TV, Setup Box, Desktops, workstations, servers, Automotive, Embedded systems, Network switches, and Enterprise computing…
In addition to PCIe IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, Display Port, MIPI (CSI, UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
Availability:
These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo
About T2M:
T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com
|
T2M Hot IP
- Bluetooth Dual Mode v5.4 / IEEE 15.4 PHY/RF IP in TSMC22nm ULP
- GNSS Ultra low power (GPS, Galileo, GLONASS, Beidou3, QZSS, IRNSS, SBAS) Digital ...
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven)
- MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
Related News
- Augment your Peripheral slot's performance with the Low Power and High Throughput PCIe 4.0 PHY IP Cores in 12FFC with matching PCIe 4.0 Controller IP Cores
- Enhance your High-Density data processing capabilities to new heights with the USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP Core interface in 28HPC+/HPC process technology
- PCIe 5.0 & PCIe 4.0 PHYs and Controller IP Cores are available for immediate licensing to maximize your Interface speed for complex SoCs
- USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP Cores for High Bandwidth, Low Power data communication in PCs, Mobiles, SSDs, and other Multimedia Devices.
- Introducing USB 3.0, PCIe 2.0 and SATA 3.0 Combo PHY IP Cores to empower Next Gen Connectivity Chipsets
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |