Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0

Tewksbury, MA., October 25, 2022 — Avery Design Systems, the leader in functional verification solutions, continues to drive the industry adoption of the Compute Express Link^TM (CXL™) open industry-standard interconnect, introducing new features in its QEMU software virtual machine emulator based Linux host and SoC RTL co-simulation solution for system-level verification of complete CXL HW-SW systems.

Enhancements to QEMU virtual machine emulator

Avery continues to push the leading edge of CXL adoption with new enhancements specifically aimed at enabling pre-silicon validation of the upcoming 3.0 version of the standard, which will double bandwidth with the same latency as previous versions. The most recent enhancements expand the capabilities of its QEMU-CXL platform and include the Latest linux kernel 6.0.1 supporting CXL and interoperability tests such as using cxl-cli for memory pooling provisioning, resets and Sx states, and Google stressapptest using randomized traffic from processor to HDM creating realistic high workload situations.

The entire platform supports pre-silicon design of SoCs leveraging version 3.0 and prior 2.0/1.1 versions of the CXL standards.

Co-simulating the SoC RTL with a QEMU open software virtual machine emulator environment allows software engineers to natively develop and build custom firmware, drivers, and applications and run them unaltered as part of a comprehensive system-level validation process using the actual SoC RTL hardware design. In a complementary manner, hardware engineers can evaluate how the SoC performs through executing UEFI and OS boot and custom driver initialization sequences in addition to running real application workloads and utilize the CXL protocol aware debugging features of the VIP to effectively investigate any hardware related issues.

“Combined with our CXL compliant VIP, our QEMU CXL virtual platform and VIP co-simulation enables complete CXL system-level bring-up of SoCs in a Linux environment. With this approach customers can address new CXL 3.0 design and verification challenges even when no mainstream commercial platforms support the latest standards,” said Chris Browy, vice president sales/marketing at Avery.

“Avery’s CXL virtual platform and VIP co-simulation solution helped reduce our validation time as we were able to perform extensive pre-silicon verification on our Leo Memory Connectivity Platform that supports CXL 2.0 and 1.1 technologies, and we are ready for real-world deployment. We look forward to utilizing a similar approach as we evolve next generation CXL designs,” said Suresh Sankaralingam, head of DV and Emulation, Astera Labs.

Availability & Additional Resources

CXL VIP for CXL 3.0/2.0/1.1 is available today.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

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