RISC-V Summit 2022: Codasip to showcase processor customization, and safety and security solutions
Munich, Germany - 29 November 2022 - At RISC-V Summit 2022, Codasip, the leader in processor design automation and RISC-V processor IP, will present solutions for implementing safety and security in RISC-V IP. In addition, the company will demonstrate the benefits of its unique processor customization offering. The technology will be presented as demos in booth PG2 and in conference sessions.
This December, the #RISCV community – including the technical, industry, domain, and special interest groups who define the architecture’s specifications – will be in San Jose, California for four days of technology breakthroughs, industry milestones, tutorials, and relationship-building. The event is being produced in a hybrid format, with both in-person and virtual participation available. Codasip is a platinum sponsor of the summit, and will be presenting the following sessions:
On Tuesday, December 13, 10:35am – 10:45am, Ron Black, CEO is presenting on the topic Avoiding Murphy’s Law and Satan’s Law without selling your soul.
Tuesday, December 13, 3:30pm – 3:40pm, Paul Elliott, Safety and Security Architect will do a live demo of a RISC-V dual lock-step implementation for safety and security applications.
On Wednesday, December 14, 4:25pm – 5:10pm, Keith Graham, VP University Program and Customer Experience, will be part of the panel discussion RISC-V in education and training: Successes and gaps.
Anyone interested to learn more about Codasip’s offering can request a meeting at https://codasip.com/events/risc-v-summit-2022
Don’t miss Codasip at #RISCVSummit 2022.
About Codasip
Codasip delivers leading-edge RISC-V processor IP and high-level processor design tools, providing IC designers with all the advantages of the RISC-V open ISA, along with the unique ability to customize the processor IP. As a founding member of RISC-V International and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors.
Formed in 2014 and headquartered in Munich, Germany, Codasip currently has R&D centers in Europe and sales representatives worldwide. For more information about our products and services, visit www.codasip.com. For more information about RISC-V, visit www.riscv.org.
|
Codasip Hot IP
Related News
- XtremeEDA to enable IoT security deployment with Crypto Quantique's solution using Codasip's RISC-V processor
- Codasip to Offer Secure Boot Solutions with Veridify Tools
- Synopsys Advances Automotive Security with Industry's First IP Product to Achieve Third-Party Certification for ISO/SAE 21434 Cybersecurity Compliance
- Codasip introduces best-in-class RISC-V core for power-efficient applications
- MerlinTPS Partners with Bluespec to Provide Urgently Needed GPS Augmentation and Backup Without Satellites
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |