Atrenta Introduces First Intelligent Constraint Analyzer; Helps Eliminate Chip Integration Timing Problems

New Tool Finds Problems Often Not Discovered Until After Synthesis and Place & Route

SAN JOSE, CA. --Apr 14, 2003-- Atrenta® Inc, the Predictive Analysis® Company, announced that SpyGlass® Constraints, the first chip design tool that checks design constraint files, including SDC constraints, early in the design cycle to eliminate time-consuming downstream iterations throughout the design cycle - from synthesis all the way through place and route. While constraint files can be as complex and lengthy as RTL code files and cause just as many problems as RTL coding issues, no tool has offered the ability to check constraint files, until now. Constraints files are critical for many design tools and provide valuable guidance for timing closure.

"SDC constraint files are critical for expressing design intent for synthesis and static timing analysis," said Daren Bledsoe, Design Section Manager for Agilent's ASIC Products Division. "Checking the RTL against the SDC constraints for completeness and consistency early in the design cycle minimizes customer iterations in Agilent's RTL handoff flow."

"Constraint analysis is an area that has been largely ignored by EDA companies, yet it is critical to an efficient design flow," stated Ghulam Nurie, Senior Vice President Marketing & Business Development, Atrenta Inc. "We developed SpyGlass Constraints as a natural complement to the rest of our SpyGlass product line, which analyzes RTL code and detects downstream problems. Now, with the complete SpyGlass family, design teams can cover all the bases - the RTL code, gate level netlist and the constraints - and feel sure that they're doing everything they can up front to eliminate time consuming iterations."

Block-Level Constraint Analysis
Today's large chip designs are divided into blocks that are given to different design teams. Each team is given a target set of constraints for that particular block. As each block is coded in VHDL or Verilog and constraints files are developed or modified, designers can use SpyGlass Constraints to check their constraint files before they even start to synthesize their designs. By finding and fixing problems with their constraints early, they can eliminate synthesis iterations and the need to re-verify parts of the design.

At the block level, SpyGlass Constraints can find several types of issues. Many of these issues relate to timing, a critical challenge for most designs. The product checks the consistency and completeness of the constraints in the following areas where constraints play critical roles in RTL design:

• Clock characteristics (waveform, latency, and transition times).
• All clocks must be constrained, and generated clocks must be consistent with specified source clocks.
• Input and output constraints are consistent with destination or sourcing clocks.
• Drive (load) specifications are set for all inputs or outputs.
• Timings exceptions are specified on stable points in the design.

Full-Chip Constraint Analysis
As the blocks are integrated into the total chip design, block-level constraints (particularly timing exceptions) are merged and there are more opportunities for problems. A large design may require tens of thousands of constraints. Methods to check constraint correctness to date have been, at best, ad hoc.

"During synthesis or timing analysis, questionable constraints are frequently not reported as errors because what is an error depends on the design objective," stated Dr. Bernard Murphy, Atrenta's Chief Technology Officer. "Constraint problems are often detected only after detailed timing analysis, and sometimes during physical design. Detecting these problems can require sophisticated scripting and days or weeks of debug. Customers are telling us this approach is simply not scaling with larger designs, especially in RTL Handover or ASIC interface environments where the implementer is not intimately familiar with all aspects of the design."

Constraints at block boundaries are particularly challenging because they can only be tested when the blocks are put together. There are many opportunities for constraint problems as blocks are integrated. A block team may define multi-cycle paths or false paths on points that disappear in top-down re-synthesis. Every synthesis run produces very different results, and new top-down synthesis runs often require extensive rework. It is very challenging for the chip integration team to verify that all timing exceptions have been transferred correctly from the block level to the full-chip level. With SpyGlass Constraints, many of these issues can be detected and resolved before they become problems in integration.

New Visualization Tool
SpyGlass Constraints also includes a new visualization tool, which creates timing diagrams representing the constraints, helping the user check assumptions associated timing requirements.

Availability
SpyGlass Constraints is in Beta testing. Production shipments are expected in June of 2003. Pricing for SpyGlass Constraints starts at $40,000.

About SpyGlass
SpyGlass® uses a unique predictive analysis technique to perform detailed structural analysis on Verilog and VHDL RTL in order to detect complex design problems early in the design cycle, resulting in reduced development costs, lower risk and early time to market. SpyGlass' fast-synthesis engine creates a structural representation of the design allowing the most comprehensive and accurate analysis of RTL to detect problems not normally visible in the RTL. Problems detected include clock domain crossings, synchronization, and timing issues, testability problems, SoC integration requirements, RTL-handoff, design reuse, clock/reset requirements, and coding styles. SpyGlass quickly pinpoints critical problems not generally found until after lengthy simulation and synthesis runs, such as combinational loops, levels of logic and fanout violations, tri-state bus decoding errors, inefficient use of resources and much more. SpyGlass was selected by EDN magazine as one of the Top 100 products for 2002 and also received the "LSI Design of The Year 2002" award by Japan's Semiconductor Industry News.

About Atrenta
Atrenta enhances the verification process through its ground-breaking Predictive Analysis technology which accelerates the design of ASICs, SoCs and FPGAs by enforcing downstream requirements upfront. Its award-winning SpyGlass family of predictive analysis products performs detailed structural analysis at design creation stage (Verilog and VHDL RTL) to detect complex design problems that are not easily detected with conventional verification methods. SpyGlass has been widely adopted by more than 50 of the world's leading electronics companies, including eight of the top ten semiconductor companies. Atrenta was chosen by Venture Reporter as one of the top 100 venture-backed companies for 2002.

Atrenta employs over one hundred people worldwide and is headquartered in San Jose, California, with European offices in England and France, a research and development center in India, and sales and support distributors in Central Europe, India, Israel, Japan, Korea, Singapore, Taiwan, and United Kingdom. For further information, visit the Atrenta website at www.atrenta.com or call 408-453-3333.