Secure-IC & Trasna are introducing a revolutionary PUF solution that eliminates the need of enrollment phase
Cesson-Sévigné (France) / Cork (Ireland) -- February 23, 2023 – Secure-IC, the rising leader and unique global provider of end-to-end cybersecurity solutions for embedded systems and connected objects, and Trasna, an IoT secure hardware and software specialist, announce today they have succeeded to offer a groundbreaking Physically Unclonable Function (PUF) solution. Working in tandem, Secure-IC and Trasna have successfully developed an innovative PUF IP that can generate one or several unique IDs or keys without the need for any cryptographic enrollment phase. This PUF IP complies with ISO/IEC 20897 and is integrated into a Trasna All-in-One ultra-efficient narrowband NB-IoT SoC (System-on-Chip) and will be integrated in the full wireless SoC family dedicated to IoT.
The market for narrowband IoT is expected to continue to grow in the coming years as more devices and applications become connected. Security is a paramount importance for this technology because it is being used to connect a vast array of devices and services, and any security breach could have severe consequences.
In modern System on Chips, PUFs (Physically Unclonable Functions) have been introduced to generate specific key numbers for a chip. While this technology ensures a high level of security, it is challenging to guarantee a low probability of identical IDs across separate chips. As a result, about 90% of PUF technologies cannot function independently due to their subpar performance. They require extensive an enrollment phase and a rebuilding phase, to improve the quality of the ID or key.
This presents a significant challenge for chip manufacturers as:
- PUF IPs cannot serve as a reliable security source for starting the chip without enrollment phase for the cryptographic key construction.
- Enrollment phase is a costly process since each chip must be personalized on its own. The process of enrollment consists in the following phases: lengthy measurements, characterization, helper data derivation, and eventually helper data programming. This interactive protocol is incompatible with the efficient personalization steps required at test stage when producing chips at scale.
- The need for enrollment leaves the door open to hackers trying to subvert the enrollment, e.g., by forcing all the bits of the key to be the same.
Therefore, chip manufacturers face a considerable obstacle in implementing PUF technology due to the need for extensive an enrollment phase and a rebuilding phase, high costs, and concerns regarding the system’s vulnerability to attacks.
Secure-IC and Trasna have collaborated to develop a PUF IP that does not require any enrollment phase nor a rebuilding phase. By leveraging Secure-IC’s PUF generation method and Trasna’s expertise, they have managed to create a PUF IP capable of generating one or a few unique IDs or keys working straight out of the box.
With this breakthrough, the PUF IP can now serve as the foundation for secure booting of the chip, lifecycle management, seed of Root of Trust, and unique ID. This represents a significant game-changer in the use of PUF IPs, as it allows the ID/Key to be readily available upon chip start-up.
Developed by Trasna, the All-in-One ultra-efficient NB-IoT SoC, includes this new revolutionary secure PUF solution from Secure-IC that will offer first a fully integrated NB-IoT platform for low-power wide-area networks (LPWANs) embedding RISC-V cores for application, security and radio and enabling iSIM and GNSS. It has been built around large numbers of IoT devices that are expected to operate for many years from a single battery. Target applications include smart cities, smart utility metering, security, logistics, and Industry 4.0.
“Trasna’s main objective is to develop and industrialize All-in-One secure System on Chip (SoC) solutions that require only a few external components to enable the extensive deployment of 5G/massive IoT, while ensuring the utmost security” said Yves Fusella, CTO of Trasna. “Collaborating with Secure-IC has been an excellent experience, as they truly understood our security requirements and what was necessary to align the PUF with our solutions. It has been a pleasure working together to develop this game-changing technology”.
“It is an exciting opportunity to partner with Trasna and to ease adoption of PUF in chips to be deployed in large scale” said Sylvain Guilley, CTO of Secure-IC. “This agreement acknowledges the portability, the genericity and the compliance of our security products”.
Both companies will showcase their solutions at the upcoming MWC Barcelona event, that will take place 27 February – 02 March. Secure-IC will be at booth 5B41-2 and Trasna at the Congress Square Stand CS54.
|
Secure-IC Hot IP
- Securyzr integrated Security Services Platform (iSSP). Complete end-to-end secur ...
- Secure-IC Securyzr(TM) Cyber Escort Unit IP provides real time detection of ser ...
- Securyzr iSE 100/300/700/900 series by Secure-IC: integrated Secure Element (iSE ...
- Securyzr Digital True Random Number Generator (TRNG) by Secure-IC, compliant wit ...
- Securyzr iSE 700 series by Secure-IC: an integrated Secure Element (iSE) for aut ...
Related News
- Intrinsic ID Signs Representation Agreement with Kaviaz Technology to Extend the Commercial Reach of its Physical Unclonable Function (PUF) Security IP Solutions in Taiwan
- Intrinsic ID Partners with Jupiter Semi to Expand its Physical Unclonable Function (PUF) Security IP into China
- Xilinx Addresses Rigorous Security Demands at Fifth Annual Working Group for Broad Range of Applications
- Microsemi Steps Up Its Cyber Security Leadership in FPGAs: SmartFusion2 SoC FPGAs and IGLOO2 FPGAs Enhanced with Physically Unclonable Function Technology
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |