Defacto will celebrate its 20th anniversary at DAC with customer presentations and major technical announcements
Grenoble, France -- June 7, 2023 -- Save the date! Defacto will be celebrating its 20th anniversary when exhibiting at DAC this July 2023 in San Francisco! Several customer testimonials will be held every day at the Defacto booth (#1541) to showcase how Defacto’s design solution helps reducing engineering pain when building among the largest SoC chips in the market pre-synthesis.
Among Customer presentations several testimonies from TOP5 semiconductor companies. This Anniversary celebration will also coincide with major technical announcements of Defacto’s SoC Compiler V10 Major Release: performance improvement, Python-based higher automation, unified management of RTL, IP-XACT, UPF, SDC, LEF/DEF, etc. In addition, Defacto experts will present the new capabilities and features such as:
- Press-button Subsystem generation of top-level RTL/IP-XACT, UPF, etc. given user XLS specification
- Physical assistance to help RTL designers and SoC design architects capture physical design information and build physically-aware RTL, UPF, …
- DFT and Test Point Exploration at RTL to automatically get the best tradeoff coverage/area when inserting test points while ensuring high test coverage figures.
To attend Defacto’s customer presentations and Release presentations, please contact Defacto on their website: https://defactotech.com/contact
About Defacto’s SoC Compiler
Defacto’s SoC Compiler is a complete SoC integration platform, multi-dimensional and pre-synthesis with a high level of automation taking into consideration all the design information including RTL, IP-XACT, timing constraints, power, physical, and test. Before logic synthesis, SoC Compiler enables full implementation capabilities towards IP and connectivity insertion, design editing, and views generation with real-time monitoring of the integration progress. This enables SoC creation in minutes and maximizes design reuse from existing projects. In addition, several APIs are provided (Tcl, Python, C++, Java, etc.) to help in the development of internal and custom design platforms.
About Defacto Technologies
Founded in 2003, Defacto Technologies is a chip design software company providing breakthrough System on Chip design solutions to enhance design integration, design verification, and also the Signoff of IP cores, subsystems and large SoCs.
By adopting Defacto’s SoC Compiler design solutions, major semiconductor companies are continuously moving from traditional and painful SoC design tasks to a fully automated design methodology. The related ROI has been proven for hundreds of projects.
|
Related News
- Crypto Quantique signs first major client in Taiwan
- OIF Marks 25th Anniversary, Launches New Physical & Link Layer Working Group Electrical Project and Adds 112G VSR Clause to CEI 5.0 IA at Q1 Technical and MA&E Committees Meeting
- Arteris IP Achieves Major Milestone: 100th Customer
- Defacto Technologies Announces Synapse Design in collaboration with a major semiconductor company Reduces Simulation Time by 5X When using Defacto's RTL Design Solutions
- GUC Announces 20th Anniversary
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |