Samsung Foundry Certifies Cadence Virtuoso Studio Flow to Automate Analog IP Migration on Advanced Process Technologies
SAN JOSE, Calif.— June 28, 2023 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of a certified node-to-node design migration flow based on the new generative AI-powered Cadence® Virtuoso® Studio. The flow is compatible with Samsung Foundry’s advanced nodes. Cadence and Samsung jointly developed this new generative design migration flow to simplify and automate the process, providing mutual customers with up to a 2X productivity boost so they can get to market faster.
The Virtuoso Schematic Editor, part of the Virtuoso Studio, automatically maps a source schematic’s instances, parameters, pins and wiring from one process technology to another. The mapped schematic is optimized and verified using the Virtuoso ADE simulation environment and AI-enabled circuit optimization technology to ensure the updated schematic meets all necessary design specifications.
The Virtuoso Layout Suite, part of the Virtuoso Studio, supports the reuse of existing layouts on a given process technology to quickly regenerate a migrated layout on a new process technology through custom place and route automation. The suite automatically recognizes and extracts groups of devices in an existing layout and migrates them into the new template. Similar relative placement and routing are maintained in the target layout, saving weeks of manual effort that would otherwise be needed to recreate the layout, while taking advantage of the size-shrink benefit of the new target process.
“Designers are up against more rigorous deadlines than ever before, so finding creative ways to become more efficient is a top priority,” said Sangyun Kim, vice president of Foundry Design Technology team at Samsung Electronics. “Through our ongoing collaboration with Cadence, we’re providing customers with an accelerated path to migrate from node to node by providing access to the Cadence Virtuoso Studio flow and Samsung advanced-node technologies.”
“Through this latest collaboration with Samsung, our joint customers have access to our new generative AI-powered Virtuoso Studio, which provides automation capabilities that make it easier to quickly move from one process technology to another,” said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. “With Samsung’s advanced process technologies and the Cadence flows, designers can benefit from increased productivity and ultimately deliver high-quality designs to market faster.”
Cadence Virtuoso Studio supports the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence. To learn more about Virtuoso Studio, please visit http://www.cadence.com/go/virtuosostudiosf.
About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
|
Cadence Hot IP
Related News
- Cadence Custom/Analog Design Migration Flow Accelerates Adoption of TSMC Advanced Process Technologies
- Cadence AI-Based Virtuoso Studio Certified for Samsung Foundry PDKs for Mature and Advanced Nodes
- Cadence's New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies
- Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5/3D Chip Designs
- Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |