Xpeedic Launches High-Speed Digital Signal Integrity, Power Integrity Suite at Design Automation Conference
SAN FRANCISCO –– July 10, 2023 –– Xpeedic today launched its high-speed digital signal integrity and power integrity (SI/PI) suite with significant features and upgrades to advanced packaging and high-speed design domains as the 60th Design Automation Conference (DAC) opens at Moscone Center West here.
The Xpeedic EDA 2023 Suite includes 2.5D and 3D signal integrity and power integrity simulation for advanced packaging, along with three platforms to support 3D Electromagnetic (EM) simulation, multi-domain co-simulation and high-speed system simulation.
Continuous demonstrations of the EDA 2023 Suite will be shown at Xpeedic’s DAC Booth #1435 (first floor) today through Wednesday, July 12, from 10 a.m. until 6 p.m. Attendees can stop by the booth to schedule demos or meetings or by sending email to sales@xpeedic.com.
Introducing Xpeedic’s EDA 2023 Suite
Xpeedic’s announcement of the EDA 2023 Suite includes the Metis 2023 SI/PI simulation platform, Hermes 2023 EM simulation platform, Notus 2023 multi-domain platform and ChannelExpert 2023 high-speed system simulation platform. This announcement follows the introduction last month of Xpeedic’s EDA 2023 RF solution at the International Microwave Symposium (IMS).
The Metis 2023 SI/PI simulation platform, tailored for 2.5D and 3D integrated circuit (IC) advanced packaging, enables easy design analysis of 2.5D and 3DIC packaging. The latest version introduces parameterized templates for transmission lines and interposers, allowing quick pre-simulation analysis and evaluation of die-to-die (D2D) transmission lines in the interposer.
It includes layout editing through silicon via (TSV) array channel simulation, automated perfect electrical conductor (PEC) port addition, and stacking functionalities such as chip-packaging bump and wire modeling. Additionally, it supports comprehensive PI AC analysis for rapid evaluation of power integrity in 2.5D and 3DIC packaging.
Hermes 2023, a versatile EM simulation platform for chip, package, board, and connector structures, introduces a new quasi-static RLGC solver-based Hermes X3D, which is complementary to the full wave finite element method (FEM) solver-based Hermes Layered and Hermes 3D. With the adaptive meshing and XHPC distributed simulation technologies, Hermes 2023 delivers an efficient and user-friendly simulation flow with high-precision intelligent solving capabilities.
Notus 2023 multi-domain co-simulation platform includes SI/PI co-analysis, topology extraction, and thermal analysis for chip, packaging, and board designs in high-speed design. It allows rapid analysis of signal, power, and temperature to ensure compliance with defined specifications, facilitating design iterations.
ChannelExpert 2023, a high-speed system simulation platform, offers full-link analysis for time-domain and frequency-domain analysis in high-speed systems. It provides a fast, accurate, and simple way to evaluate, analyze, and resolve high-speed channel signal integrity issues. It supports IBIS and AMI model simulation, AMI model creation, GUI-based schematic-like editing, and operations. It aids design engineers in quickly constructing high-speed channels, performing channel simulations, and checking channel performance compliance with specifications.
Key features of the new version include standard AMI model creation and simulation reports based on JEDEC standards for DDR4 and DDR5X, LPDDR and LPDDR5X and others. ChannelExpert also includes advanced circuit analysis capabilities such as statistics, COM, design of experiment (DOE), yield, and Monte Carlo analysis modules.
Availability and Pricing
The Xpeedic EDA 2023 Suite for high-speed digital SI/PI and multi-physics simulation platforms is shipping now.
Pricing is available on request.
About Xpeedic
Xpeedic of Cupertino, Calif., is a leading EDA provider to accelerate designs and simulations of next generation high-frequency, high-speed intelligent electronic products. Powered by its proprietary electromagnetic, circuit, and multi-physics solver technologies, Xpeedic is addressing challenges in designing IC in advanced nodes, 3D-IC with advanced packaging, high-speed digital, and RF systems for the markets including data center, automotive, communication, mobile, and IoT. Founded in 2010, Xpeedic has offices in both U.S. and China. For more information, please visit www.xpeedic.com.
|
Related News
- Key ASIC Launches ASIC & SoC Design-to-Manufacture Services for Communications and Consumer Electronics Applications; Company Specializes in High Performance, Low Power Mixed-Signal and Digital Design
- Dolphin Technology Endorses Legend Design’s MSIM Circuit Simulator for Signal Integrity Analysis of High-Speed IO Circuits
- OEA Validated Legend’s MSIM Circuit Simulator for Quality of Results in Signal Integrity Analysis of High-Speed Interconnects
- SiSoft and Denali Team to Deliver Signal Integrity Solutions for High-Speed Memory Systems
- Artisan Debuts Comprehensive Analog, Mixed Signal And Digital IP Solutions At Design Automation Conference
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |