7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Certus Semiconductor Partners with Pragma Design for Embedded ESD Detection Technology
August 16, 2023 -- Certus Semiconductor is delighted to announce a strategic collaboration with Pragma Design, a distinguished name in innovative electronic design solutions. This partnership marks a significant leap forward in advancing Embedded Electrostatic Discharge (ESD) Detection Technology.
Embedded ESD Detection Technology Overview:
Embedded ESD Detection Technology holds paramount importance in fortifying electronic devices against Electrostatic Discharge, a latent and critical hazard to contemporary electronics. Our collaboration with Pragma Design's ESD Analysis Tool (PEAT) is focused on seamlessly integrating state-of-the-art ESD detection capabilities directly into semiconductor chips. This integration facilitates real-time monitoring and proactive defense against potential ESD incidents, thus safeguarding the integrity of electronic systems.
Wearable devices, especially in the medical field, are particularly vulnerable to ESD events. Now, more than ever, an ESD event can cause life-threatening disruptions in a system. This partnership aims to assist devices (and their wearers) in recovering gracefully from such incidents.
Rationale Behind the Partnership:
Certus Semiconductor is dedicated to innovation and continuous improvement in chip-level IO cell performance. Pragma Design's expertise in system-level design and analysis and their disruptive technological advancement of PEAT technology align perfectly with our goal of helping semiconductor suppliers deliver robust, cost-effective, and high-performance solutions.
Advantages of Embedded ESD Detection:
- Preventive Safeguarding: Real-time monitoring empowers devices to promptly enact protective measures upon detecting an ESD event, mitigating operational disruptions.
- Enhanced Reliability: Implementing embedded ESD detection technology significantly reduces the risk of ESD-induced failures, thereby increasing device reliability and lifespan.
- Real Sustainability: An ESD failure of a 2-cent component triggers downtime and replacement costs. It also results in an often overlooked doubling of the pollution footprint generated by manufacturing and shipping an entire replacement system.
- Economical Viability: By averting ESD-related setbacks, manufacturers can reduce costly warranty claims, mitigate injury risks, and eliminate the need for product recalls.
The Road Ahead:
Pragma and Certus are combining our system-level and chip-level ESD IP and expertise to develop a comprehensive suite of embedded ESD detection solutions. Expect upcoming updates on our progress and breakthrough innovations arising from this synergy.
We are forging a more reliable and sustainable technological future as we adapt this ESD detection technology for real-world production beyond academic exploration.
|
Certus Semiconductor Hot IP
Related News
- Certus Semiconductor releases ESD library in GlobalFoundries 12nm Finfet process
- Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+
- X-FAB Releases Embedded Flash Solution on its 110nm Automotive BCD-on-SOI Technology
- AI Software Startup Moreh Partners with AI Semiconductor Company Tenstorrent to Challenge NVIDIA in AI Data Center Market
- Certus Semiconductor releases I/O library in TowerJazz's 65nm process
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |