Synopsys and TSMC Collaborate to Accelerate 2nm Innovation for Advanced SoC Design with Certified Digital and Analog Design Flows
Design Flow Achieved Multiple Successful Test Chip Tape-Outs on TSMC N2 Process; Broad IP Portfolio in Development to Speed Time to Market
SUNNYVALE, Calif., Sept. 25, 2023 -- Synopsys, Inc. (Nasdaq: SNPS) today announced that its digital and custom/analog design flows are certified for TSMC's N2 process technology, enabling faster delivery of advanced-node SoCs with higher quality. Both flows are seeing strong momentum, with the digital design flow achieving multiple tape-outs and the analog design flow adopted for several design starts. The design flows, powered by the Synopsys.ai™ full-stack AI-driven EDA suite, deliver a significant lift in productivity. Synopsys Foundation and Interface IP in development for the TSMC N2 process will help reduce integration risk and speed time to market for advanced HPC, AI, and mobile SoCs. Additionally, Synopsys AI-driven design technologies, including Synopsys DSO.ai™, are enabled to fast-path the optimization of N2 design to improve the power, performance, and area.
"High quality-of-results and faster time to market for advanced SoC designs are hallmarks of TSMC's and Synopsys' longstanding collaboration," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "We work closely with our design ecosystem partners like Synopsys to deliver a full-spectrum of best-in-class solutions for TSMC's most advanced process technologies, providing our mutual customers a clear advantage in meeting the silicon demands of high-performance applications, along with a proven path to rapidly migrate their designs from node to node."
"The Synopsys digital and analog design flows for the TSMC N2 process represent a significant investment by Synopsys across the full EDA stack, helping designers jumpstart their N2 designs, differentiate their SoCs with increasingly better power, performance, and chip density, and accelerate their time to market," said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. "Our close collaboration with TSMC through every generation of TSMC's process technologies enables us to deliver unmatched EDA and IP solutions that customers need to innovate and strengthen their competitive advantage."
Efficient Reuse of Designs from Node to Node
The Synopsys analog flow enables efficient reuse of designs from node to node on TSMC advanced processes. As part of the certified EDA flows, Synopsys provides interoperable process design kits (iPDKs) and Synopsys IC Validator™ physical verification for full-chip physical signoff.
Availability
The certified EDA flows are available now.
- For information about the digital design flow, visit: Synopsys Digital Design Family
- For information about the analog design flow, visit: Synopsys Custom Design Family
Additional Resources
- For more information about the Synopsys AI-driven design technologies, including Synopsys DSO.ai™, visit www.synopsys.com/ai
- News Release: Synopsys and TSMC Advance Analog Design Migration with Reference Flow Across Advanced TSMC Processes
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry's broadest portfolio of application security testing tools and services. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at www.synopsys.com.
|
Related News
- Synopsys Achieves Certification of its AI-driven Digital and Analog Flows and IP on Samsung Advanced SF2 GAA Process
- Synopsys and Intel Foundry Accelerate Advanced Chip Designs with Synopsys IP and Certified EDA Flows for Intel 18A Process
- Cadence Digital and Custom/Analog Design Flows Certified for TSMC's Latest N3E and N2 Process Technologies
- Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes
- Synopsys and TSMC Accelerate 2.5D/3DIC Designs with Chip-on-Wafer-on-Substrate and Integrated Fan-Out Certified Design Flows
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |