English
Axiomise Heads to Silicon Valley Next Week for RISC-V Summit North America
Will Showcase formalISA Custom App for Open-Source and Commercial RISC-V Processors
LONDON –– November 1, 2023 –– Axiomise will showcase its portfolio of cutting-edge formal verification solutions that includes training, consulting, services and its custom app formalISA® during RISC-V Summit North America November 7 and 8 in Silicon Valley.
The formalISA® app launched earlier this year is used to formally verify numerous open-source and commercial RISC-V processors, proving the absence of bugs in out-of-order and in-order cores. End users are able to get formal verification results on any RISC-V core by pushing a few buttons and using any formal verification tool.
Axiomise will be in booth #S11 and will feature live demonstrations of the formalISA app and reinforce how it is making formal normal. Axiomise also unveiled earlier this year its RISC-V Studio Portal that displays and explains in detail real-world applications and product demonstrations of how bugs can be caught using formal verification methods.
The RISC-V Summit North America exhibits will be open Tuesday, November 7, from 10:45 am until 7 pm, and Wednesday, November 8, from 10:45am through 4:15 pm at the Santa Clara Convention Center in Santa Clara, Calif. Registration is open.
About formalISA
Axiomise’s formalISA is intelligent debug combined with exhaustive proofs and coverage for end-to-end formal verification. The push-button formal verification solution verifies the architecture and micro-architecture of RISC-V processor cores. It is in use in production environments to formally verify numerous open-source and commercial RISC-V processors by identifying deep corner-case bugs and mathematically proving the absence of bugs on complex out-of-order and in-order cores.
About Axiomise
Axiomise is accelerating formal verification adoption through its unique combination of training, consulting, services and specialized verification solutions for RISC-V. Axiomise was founded by Dr. Ashish Darbari, FBCS, FIETE, DPhil (Oxford), who has been a formal verification practitioner for more than two decades with 60 patents in formal verification and over 70 publications.
|
||||||
Related News
- Andes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023
- Think Silicon demonstrates early preview of Industry's first RISC-V ISA based 3D GPU at the RISC-V Summit
- Silex Insight expands into North America with opening of Silicon Valley office
- M2000 Opens Silicon Valley Office Serving eFPGA Customers Throughout North America
- Virage Logic Recognized as one of the Fastest-growing Companies in Silicon Valley and North America by Deloitte & Touche
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Qualitas Semiconductor Signs IP Licensing Agreement with Edge AI Leader Ambarella
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura's Cyberthreat Intelligence Tool
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Alchip Opens 3DIC ASIC Design Services
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
|
E-mail This Article | 
|
|
Printer-Friendly Page |