Xilinx gains Insight to create UDP core

Xilinx gains Insight to create UDP core; MIPS, Tality in SoC linkup

Xilinx gains Insight to create UDP core; MIPS, Tality in SoC linkup
By Michael Santarini, EE Times
July 24, 2001 (6:04 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010723S0027

Xilinx Inc. and Insight Electronics have released a User Datagram Protocol (UDP) stack core optimized for Xilinx FPGAs. Separately, Xilinx also said it has licensed the 64-bit RapidIO technology from Praesum Communications.

The UDP stack core can be used to create low-cost consumer products such as voice-over-Internet Protocol (VoIP) phones, Internet intercoms, remote security monitors, Internet-based voice recorders and simple thin clients for home networking, Xilinx and Insight said. The core, optimized for hardware FPGA implementation, has what the co-developers say is a unique feature: It exhibits zero stack latency and can therefore operate at line speeds.

Xilinx and Insight's MemecCore Division have used the UDP stack core in a low-cost consumer VoIP reference design, based on a single Spartan-II FPGA. Xilinx said it can also be implemented in its Virtex, Virtex-II and Virtex-E FPGAs.

The reference design, available in kit s, contains two VoIP hardware boards, headsets and power supplies, plus technical support from the Insight Electronics Reference Design Center. It costs $995 and includes a single-project license for the UDP netlist core. The UDP stack core can be bought separately for $695. Both are available now. Customer-specific intellectual-property integration, modifications and application support is available via Insight Design Services. Visit www.insight-electronics.com/spartan_IIVoIP.

Meanwhile, Xilinx has licensed Praesum Communications' RapidIO technology to address the demand for high-performance networking and equipment with a 64-bit implementation capable of scaling to OC-192 line rates, or 10 Gbits/second.

The core complies with Revision 1.1 of the RapidIO Physical Layer 8/16 LP-LVDS specification, the companies said, and supports a flexible buffer-management scheme suitable for both end-station and switch-port applications. It also complies with the recently released RapidIO Interconnect Specification, an open standard designed to speed communications among chips or boards within a system. The new spec defines a switch fabric-based control plane interconnect that is said to offer greater bandwidth, more scalability and higher reliability than bus-based control plane interconnects used today, yet is compatible with existing architectures.

The core was developed with Xilinx, which is exclusive licensee of Praesum's RapidIO IP technology in the FPGA market. According to the companies, it provides transmission rates hundreds of times faster than current interconnection architectures and is software-transparent.

The core is the first in a planned family of RapidIO IP and semiconductor products Praesum Communications expects to deliver this year. The company said it will also use this technology in system-level products that will be deployed in 2002. See www.praesum.com.

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A deal between MIPS Technologies Inc. and Cadence Design Systems subsidiary Tality Corp. will give embedded designers using MIPS-based technology access to Tality's system-on-chip (SoC) design capability and complementary IP. That combination will lower product-development costs of MIPS-based solutions and speed time-to-market for semiconductor manufacturers and system OEMs, the companies said.

MIPS and Tality will deploy a common design methodology for SoC integration of MIPS cores and develop a road map for application platforms based on the MIPS32 4K family of 32-bit cores and the MIPS64 5K family of 64-bit cores. In turn, Tality will offer front-end design, integration, verification and core-hardening services, and complete turnkey application platforms incorporating hardware and software elements.

Tality has begun developing bridge modules from the MIPS cores to an on-chip bus and support modules for the bus, and is enhancing its SoC verification environment to support MIPS-ba sed systems.