Eliyan Sets New Standard for Chiplet Interconnect Performance with Latest PHY Delivering Data Rate of 64Gbps on 3nm Process Using Standard Packaging
Tape out confirms most efficient and flexible UCIe-, BoW-, and UMI™-compatible multi-die solution for standard or advanced packaging implementations
SANTA CLARA, Calif. – Febraury 5, 2024 – Eliyan Corporation, credited for the invention of the semiconductor industry’s highest-performance and most efficient chiplet interconnect, today announced the successful tape out of the industry’s highest performing PHY solution for multi-die architectures, achieving bandwidth of 64Gbps/bump on a 3nm process using standard packaging. The milestone further confirms Eliyan’s ability to enable die-to-die connectivity on organic substrates – while being compatible with emerging interconnect standards - at unprecedented power, area, and latency, eliminating the need for complex silicon interposers in most applications.
Ad |
UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect ![]() TSMC CLN5FF Glink 2.0 Die-to-Die PHY ![]() 3.3v to 1.1v/200mA REG, Linear Regulator, UMC 40nm LP/RVT LowK Logic Process ![]() |
In addition to being compatible with industry interconnect standards UCIe and BoW, the NuLink PHY supports the UMI™ (Universal Memory Interconnect), a novel chiplet interconnect technology that improves Die-to-Memory bandwidth efficiency by more than 2x. UMI leverages a dynamic bidirectional PHY whose specifications are currently being finalized at OCP/ODSA.
First silicon of the company’s NuLink™ PHY in 3nm is expected in Q3 2024. Although the design will utilize standard organic/laminate packaging with 8-2-8 stack up, the highly area efficient NuLink™ PHY is bump limited and leverages innovative interference cancellation techniques to fit under not only 100um bump pitch of standard packaging, but also 55um of advanced packaging. In standard packaging it can deliver up to 4.55Tbps/mm and in advanced packaging can deliver up to 21Tbps/mm.
The successful tape-out demonstrates that Eliyan’s technology in standard organic packaging achieves similar bandwidth, power efficiency, and latency as die-to-die implementations that others can only deliver using advanced packaging technologies. In addition to allowing greater supply chain flexibility, the ability to implement chiplet-based systems in standard organic packages enables the creation of larger system-in-package (SiP) solutions, thus higher performance per power at considerably lower cost and system level power. These factors provide major gains in sustainability as well.
The tape-out includes a die-to-die PHY coupled with an adaptor layer/link layer controller IP to provide complete solutions for customers, aligned with the high-growth AI markets for HPC and edge applications. Lower TCO accommodated by utilizing standard packaging can further encourage chiplet based designs in inference and gaming segments, as well as other adjacent markets as they can be more readily qualified for aerospace, automotive, and demanding industrial markets.
“Our strategy is to provide maximum flexibility in choice of packaging options, while delivering optimal performance required for any given application. While our support for advanced packaging techniques and the use of interposers offers significant benefits, there are practical considerations that make standard packaging a more viable choice in certain cases. By being able to deliver industry leading bandwidth and maintain compatibility with emerging interconnect standards using organic substrates, we offer a best of both worlds solution that addresses the business and technical challenges of any packaging alternative,” said Eliyan’s founding CEO Ramin Farjadrad.
Raja Koduri, Founder and CEO of Mihira AI, noted, “Enabling ultra-high-bandwidth, low-power chiplet connectivity on larger-sized organic packages allows exciting options for architects. This will allow practical package construction to bring an efficient combination of compute density, memory bandwidth and capacity, at a substantial improvement in performance-per-dollar and performance-per-watt.”
For more information on Eliyan’s technology strategy for organic and advanced packaging read the white paper here.
About Eliyan
Eliyan Corporation is leading the chiplet revolution, focusing on a fundamental challenge with scaling semiconductor performance, size, power, and cost to meet the needs of high-performance computing applications. It has developed a breakthrough technology to enable the industry’s highest performing chiplet interconnect for homogenous and heterogenous multi-die architectures using either standard or advanced packaging, enabling increased sustainability through reduction in costs, manufacturing waste and power consumption. More information can be found here: www.eliyan.com
|
Related News
- Eliyan Supports Latest Version of UCIe Chiplet Interconnect Standard, Continues to Drive Performance and Bandwidth Capabilities to 40Gbps and Beyond to Help Meet the Needs of the Multi-die Era
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Eliyan Applauds Release of OCP's Latest Multi-die Open Interconnect Standard, BoW 2.0
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
- Eliyan Closes $40M Series A Funding Round and Unveils Industry's Highest Performance Chiplet Interconnect Technologies
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |