55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Proprietary Memories Are a High-Risk Endeavor
By Gary Hilson, EETimes (April 1, 2024)
Semiconductor technologies live and die by industry standards, but are there times when it makes sense to build a heavily customized—even proprietary—memory device?
The chip sector is replete with standards organizations that guide the evolution of widely adopted memory devices. JEDEC is responsible for DRAM, LPPDR, GDDR and high-bandwidth memory (HBM), among others. The Peripheral Component Interconnect Express Special Interest Group takes care of the most ubiquitous protocol for data movement, while NVMe Express and the CXL Consortium built their specifications with PCIe as their foundation. Most recently, the UCIe was developed to bring best practices to chiplets.
Graham Allan, senior manager of product marketing at Synopsys, has been in the DRAM business since 1985. “The highway of DRAM technologies is littered with the roadkill of non-JEDEC-standard memories,” he said. “If something isn’t JEDEC-standard, or if a DRAM vendor tries to go it alone with something that they want to differentiate with, it’s going to die.”
Among the many abandoned memories that never saw widespread use are Micron Technology’s HBM competitor, Hybrid Memory Cube, and Rambus’s virtual-channel DRAM, even though the latter had the backing of Intel. “These things all die because they don’t have the benefit of the entire ecosystem,” Allan said.
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