Nazomi offers standard Java accelerator
Nazomi offers standard Java accelerator
By Loring Wirbel, EE Times
January 28, 2002 (4:24 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020128S0063
SANTA CLARA, Calif. - Nazomi Technologies Inc. has parlayed its Java acceleration expertise with add-in cards and licensable intellectual property into a standard coprocessor optimized for Java byte code. The JA108 is the first of several planned devices in Nazomi's Kchip family, aimed at PDAs and 2.5- and third-generation phone handsets, and designed for local Java applet execution.
The JA108 is built for use in conjunction with any baseband DSP or integer processor, and can accommodate the designer's choice of real-time operating system or Java virtual machine. Through clever parsing of byte code into simple and complex statements, the JA108 can accelerate Java execution by 15 to 60 times, without changing system clock frequencies, said Mukesh Patel, Nazomi's chief executive officer. The processor interfaces to main system and memory buses like an SRAM interface, making it easy to add to an existing design.
When Nazomi began life as Jedi Technologies in 1998, the Java-acceleration market appeared broad enough to make soft cores the preferred vehicle for bringing Java execution into larger system-on-chip designs. But with the growing popularity of Java downloadables in packet-oriented wireless services, Nazomi saw a market for standard coprocessors.
"Many of the handset OEMs wanted to stick with existing baseband designs and add features through coprocessors, rather than design a new ASIC from scratch," said Patel. "IP [intellectual property] can take one to two years to integrate into a design, so the 108 provides a solution today."
Patel cited a study from ARC Group predicting that more than 1.1 billion wireless phones will be Java-enabled by 2006. Up to 70 percent of Java virtual machines will have Java hardware coprocessors by that time, confounding early predictions that JVMs would rely only on software.
Nazomi is not halting its licensing programs, which follow two tracks. The company offers JStar cores for Internet appliances and digital phones, and JSmart cores for smart cards. It also will continue to design reference smart cards for Java applications and standalone Java software stacks, as well as maintaining a porting service for those that need assistance linking JVMs and real-time operating systems.
When implemented in a system, the JA108 will take over execution of all Java byte code. Some 169 common instructions are implemented directly in hardware, with the rest in software. For complex byte codes without direct hardware assist, the JA108 processor takes software from the original interpreter, turns each byte code into an interpreter and makes a callback to the original software.
The processor has three power modes: an executing mode dissipating 200 microamps per megahertz, a standby mode in which caches are turned off and a sleep mode in which both caches and the Java engine are disabled.
The first version of JA108 to sample is a 10 x 10-mm 128-lead micro-BGA, with 0.8 pitch. It will be followed by a smaller processor, in a 7 x 7-mm (0.5 pitch) 128-lead micro-BGA. Price in quantities of 10,000 is $5.59.
Related News
- Startups, Nazomi Communications Inc. and Chicory Systems Inc., aim new Java chips at accelerator role
- Avery Design Systems Offers Comprehensive Verification Support for the New HBM3 Interface Standard
- PowerVR Series2NX neural network accelerator cores set the standard for performance and cost-efficiency
- SiTune Offers Production Samples of Industry's First Tuner Supporting Japan's 8K TV Satellite Standard
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |