NeuReality Boosts AI Acelerator Utilization With NAPU
By Sally Ward-Foxton, EETimes (April 4, 2024)
Startup NeuReality wants to replace the host CPU in data center AI inference systems with dedicated silicon that can cut total cost of ownership and power consumption. The Israeli startup developed a class of chip it calls the network addressable processing unit (NAPU), which includes hardware implementations for typical CPU functions like the hypervisor. NeuReality’s aim is to increase AI accelerator utilization by removing bottlenecks caused by today’s host CPUs.
NeuReality CEO Moshe Tanach told EE Times its NAPU enables 100% utilization of AI accelerators.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Flex Logix Boosts AI Accelerator Performance and Long-Term Efficiency
- Europe Leaps Ahead in Global AI Arms Race, Joining $20 Million Investment in NeuReality to Advance Affordable, Carbon-Neutral AI Data Centers
- BrainChip Boosts Space Heritage with Launch of Akida into Low Earth Orbit
- Arm shares jump 50% on AI, China boosts to results
- Rambus Boosts AI Performance with 9.6 Gbps HBM3 Memory Controller IP
Breaking News
- Ceva and Sharp Collaborate on "Beyond 5G" IoT Terminals
- Marvell Demonstrates Industry's Leading 2nm Silicon for Accelerated Infrastructure
- intoPIX Expands its offering for Medical, Human & Machine Vision Applications with TicoRAW & JPEG-XS on Lattice Low-Power FPGAs
- CAST Releases First Commercial SNOW-V Stream Cipher IP Core
- eMemory and PUFsecurity Launch World's First PUF-Based Post-Quantum Cryptography Solution to Secure the Future of Computing
Most Popular
- Semiconductor Industry Faces a Seismic Shift
- Interview with Xiphera CEO - Adapting to Market Changes
- SkyWater to Acquire Infineon's Austin Fab and Establish Strategic Partnership to Expand U.S. Foundry Capacity for Foundational Chips
- Ceva Unveils Latest High-Performance, High-Efficiency Communication DSPs for Advanced 5G and 6G Applications
- Baya Systems and Semidynamics Collaborate to Accelerate RISC-V System-on-Chip Development