Brazil and Europe sign innovative project with RISC-V technology for HPC
An international collaboration between BSC and Instituto ELDORADO will enable Brazil to develop open-source RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing
April 15, 2024 -- Pushing the boundaries of High Performance Computing (HPC) and artificial intelligence is the main objective of an innovative project that marks the beginning of the journey towards developing a Matrix Multiplication Acceleration Unit, integrated into a RISC-V processor.
The signing of the Memorandum of Understanding consolidates this partnership between Instituto ELDORADO, supported by researchers from the University of Campinas (UNICAMP), and the Barcelona Supercomputing Center – Centro Nacional de Superocmputación (BSC-CNS), one of the largest European supercomputing centers and a pioneer in the development of the open standard RISC-V in chips.
The initiative is part of the Priority Program for National Interest (PPI-Softex) and is aligned with the support of the Brazilian Ministry of Science, Technology and Innovation (MCTI) in establishing technological partnerships between Brazil and the European Union, strengthening knowledge exchange and support for excellence in research and development. Recently, Brazil became a Premier Member of the RISC-V International organization, which reinforces the country's commitment to global technological development.
Partnership for innovation
In the constantly evolving landscape of HPC, open RISC-V processors are promising to revolutionize the way we deal with computational tasks. These processors, which follow an open Instruction Set Architecture standard, without royalties and with global contribution, are gaining prominence for their customization and expandability. They offer unmatched flexibility and efficiency compared to traditional proprietary architectures.
In this project, a Matrix Acceleration Unit will be developed based on a processor that offers this flexibility and high performance. Working in collaboration with researchers from University of Campinas, BSC and ELDORADO are already discussing proposals for high-performance architectures, strengthening knowledge in RISC-V for HPC.
The Memorandum of Understanding marks the starting point of a collaborative journey to address the complex technological challenges of the 21st century and shape the future of innovation, both in Brazil and worldwide.
|
Related News
- BSC presents Sargantana, the new generation of the first open-source chips designed in Spain
- BSC and Intel announce a joint laboratory for the development of future zettascale supercomputers
- BSC, Codeplay and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM
- Europe takes a major step towards digital autonomy in supercomputing and AI with the launch of DARE project
- BSC develops four open-source hardware components based on RISC-V, contributing to open, reliable and high-performance safety-critical systems for industry
Breaking News
- Digital Core Design Unveils DPSI5 - The Next-Generation IP Core for PSI5 Communication
- Movellus and RTX's SEAKR Engineering Collaborate on Advancing Mission-Critical ASICs
- Village Island Enhances its AI100 with intoPIX's JPEG XS Technology for Advanced Real-Time Analysis
- QuickLogic Announces $1.4 Million Incremental Funding Modification for its Strategic Radiation Hardened Program
- Silicon-Proven MIPI CSI-2 & DSI-2 Tx/Rx IP Cores for your Camera & Display SoCs
Most Popular
- Intel brings 3nm production to Europe in 2025
- Qualcomm initiates global anti-trust complaint about Arm
- VeriSilicon introduces AcuityPercept: an AI-powered automatic ISP tuning system
- RISC-V in Space Workshop 2025 in Gothenburg
- X-FAB, SMART Photonics and Epiphany Design demonstrate InP-on-Silicon design flow for next-generation optical transceivers at OFC
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |